Searched refs:fcsr (Results 1 - 6 of 6) sorted by relevance

/gem5/src/arch/mips/
H A Dutility.cc120 getCondCode(uint32_t fcsr, int cc_idx) argument
123 bool cc_val = (fcsr >> shift) & 0x00000001;
128 genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val) argument
132 fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
134 bits(fcsr, cc_idx - 1, 0);
136 return fcsr;
H A Dutility.hh66 bool getCondCode(uint32_t fcsr, int cc);
67 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
68 uint32_t genInvalidVector(uint32_t fcsr);
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64uf/
H A Dmove.S8 # and the fcsr work properly.
17 TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0)
/gem5/tests/test-progs/asmtest/src/riscv/env/ps/
H A Driscv_test.h95 csrwi fcsr, 0
/gem5/tests/test-progs/asmtest/src/riscv/env/p/
H A Driscv_test.h95 csrwi fcsr, 0
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h1245 DECLARE_CSR(fcsr, CSR_FCSR)

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