Searched refs:dcachePort (Results 1 - 14 of 14) sorted by relevance

/gem5/src/cpu/simple/
H A Datomic.hh160 AtomicCPUDPort dcachePort; member in class:AtomicSimpleCPU
177 Port &getDataPort() override { return dcachePort; }
H A Datomic.cc87 dcachePort(name() + ".dcache_port", this),
141 pkt, dcachePort.cacheBlockMask);
414 dcache_latency += sendPacket(dcachePort, &pkt);
503 dcachePort.cacheBlockMask);
520 dcache_latency += sendPacket(dcachePort, &pkt);
615 dcache_latency += sendPacket(dcachePort, &pkt);
783 dcachePort.printAddr(a);
H A Dtiming.hh257 DcachePort dcachePort; member in class:TimingSimpleCPU
267 Port &getDataPort() override { return dcachePort; }
H A Dtiming.cc81 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
276 } else if (!dcachePort.sendTimingReq(pkt)) {
307 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
486 } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
622 dcachePort.cacheBlockMask);
1070 dcachePort.printAddr(a);
/gem5/src/cpu/checker/
H A Dcpu.cc69 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
130 dcachePort = dcache_port;
220 dcachePort->sendFunctional(pkt);
H A Dcpu.hh113 assert(dcachePort); variable
114 return *dcachePort;
133 MasterPort *dcachePort; member in class:CheckerCPU
/gem5/src/cpu/trace/
H A Dtrace_cpu.hh326 DcachePort dcachePort; member in class:TraceCPU
1152 Port &getDataPort() { return dcachePort; }
H A Dtrace_cpu.cc52 dcachePort(this),
58 dcacheGen(*this, ".dside", dcachePort, dataMasterID, dataTraceFile,
/gem5/src/cpu/minor/
H A Dlsq.hh114 DcachePort dcachePort; member in class:Minor::LSQ
725 MinorCPU::MinorCPUPort &getDcachePort() { return dcachePort; }
H A Dlsq.cc1206 } else if (dcachePort.sendTimingReq(packet)) {
1402 dcachePort(dcache_port_name_, *this, cpu_),
/gem5/src/cpu/o3/
H A Dlsq.hh1054 MasterPort &getDataPort() { return dcachePort; }
1110 DcachePort dcachePort; member in class:LSQ::LSQRequest
H A Dlsq_unit_impl.hh253 dcachePort = dcache_port;
1066 if (!dcachePort->sendTimingReq(data_pkt)) {
H A Dlsq_impl.hh75 dcachePort(this, cpu_ptr),
108 thread[tid].setDcachePort(&dcachePort);
H A Dlsq_unit.hh397 MasterPort *dcachePort; member in class:LSQUnit

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