Searched refs:cpu_pkt (Results 1 - 5 of 5) sorted by relevance

/gem5/src/mem/cache/
H A Dnoncoherent_cache.cc150 NoncoherentCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, argument
156 assert(cpu_pkt->needsResponse());
161 PacketPtr pkt = new Packet(cpu_pkt->req, MemCmd::ReadReq, blkSize);
168 cpu_pkt->print());
H A Dnoncoherent_cache.hh122 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
H A Dcache.cc480 Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, argument
485 assert(!cpu_pkt->isEviction());
489 if (cpu_pkt->req->isUncacheable() ||
490 (!blkValid && cpu_pkt->isUpgrade()) ||
491 cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) {
497 assert(cpu_pkt->needsResponse());
505 assert(cpu_pkt->cmd != MemCmd::WriteLineReq || is_whole_line_write);
517 cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq;
518 } else if (cpu_pkt
[all...]
H A Dcache.hh152 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
H A Dbase.hh608 * below, or nullptr if the current request in cpu_pkt should just
611 * @param cpu_pkt The miss packet that needs to be satisfied.
614 * even if the request in cpu_pkt doesn't indicate that.
619 virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,

Completed in 14 milliseconds