Searched refs:cpuInstDataPort (Results 1 - 6 of 6) sorted by relevance

/gem5/src/cpu/testers/rubytest/
H A DRubyTester.py37 cpuInstDataPort = VectorMasterPort("cpu combo ports to inst & data caches") variable in class:RubyTester
/gem5/configs/learning_gem5/part3/
H A Dtest_caches.py103 tester.cpuInstDataPort = seq.slave
107 tester.cpuInstDataPort = seq.slave
/gem5/tests/configs/
H A Drubytest-ruby.py107 tester.cpuInstDataPort = ruby_port.slave
H A Dgpu-randomtest-ruby.py122 tester.cpuInstDataPort = ruby_port.slave
/gem5/configs/example/
H A Druby_random_test.py133 tester.cpuInstDataPort = ruby_port.slave
H A Druby_gpu_random_test.py158 tester.cpuInstDataPort = ruby_port.slave

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