/gem5/ext/mcpat/cacti/ |
H A D | uca.cc | 41 : dp(dyn_p), bank(dp), nbanks(g_ip->nbanks), refresh_power(0) { 42 int num_banks_ver_dir = 1 << ((bank.area.h > bank.area.w) ? _log2(nbanks) 71 htree_in_add = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 75 htree_in_data = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 79 htree_out_data = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 87 htree_in_add = new Htree2(g_ip->wt, bank [all...] |
H A D | Ucache.cc | 44 #include "bank.h" 247 int num_act_mats_hor_dir = uca->bank.dp.num_act_mats_hor_dir; 248 int num_mats = uca->bank.dp.num_mats; 249 bool is_fa = uca->bank.dp.fully_assoc; 250 bool pure_cam = uca->bank.dp.pure_cam; 265 ptr_array->mat_height = uca->bank.mat.area.h; 266 ptr_array->mat_length = uca->bank.mat.area.w; 267 ptr_array->subarray_height = uca->bank.mat.subarray.area.h; 268 ptr_array->subarray_length = uca->bank.mat.subarray.area.w; 279 ptr_array->delay_input_htree = uca->bank [all...] |
H A D | uca.h | 39 #include "bank.h" 52 Bank bank; member in class:UCA
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H A D | cacti.mk | 27 SRCS = area.cc bank.cc mat.cc main.cc Ucache.cc io.cc technology.cc basic_circuit.cc parameter.cc \
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/gem5/src/mem/ruby/structures/ |
H A D | BankedArray.cc | 58 unsigned int bank = mapIndexToBank(idx); local 59 assert(bank < banks); 61 if (busyBanks[bank].endAccess >= curTick()) { 74 unsigned int bank = mapIndexToBank(idx); local 75 assert(bank < banks); 77 if (busyBanks[bank].endAccess >= curTick()) { 78 if (busyBanks[bank].startAccess == curTick() && 79 busyBanks[bank].idx == idx) { 88 busyBanks[bank].idx = idx; 89 busyBanks[bank] [all...] |
/gem5/ext/drampower/src/ |
H A D | CAHelpers.cc | 87 bool CommandAnalysis::isPrecharged(unsigned bank) argument 89 return bank_state[bank] == BANK_PRECHARGED; 92 void CommandAnalysis::printWarningIfActive(const string& warning, int type, int64_t timestamp, unsigned bank) argument 95 printWarning(warning, type, timestamp, bank); 99 void CommandAnalysis::printWarningIfNotActive(const string& warning, int type, int64_t timestamp, unsigned bank) argument 102 printWarning(warning, type, timestamp, bank); 106 void CommandAnalysis::printWarningIfPoweredDown(const string& warning, int type, int64_t timestamp, unsigned bank) argument 109 printWarning(warning, type, timestamp, bank); 113 void CommandAnalysis::printWarning(const string& warning, int type, int64_t timestamp, unsigned bank) argument 117 ", Bank: " << bank << end [all...] |
H A D | CommandAnalysis.h | 69 // Number of activate commands per bank 71 // Number of precharge commands per bank 73 // Number of reads commands per bank 75 // Number of writes commands per bank 146 // Possible bank states are precharged or active 210 void handleAct( unsigned bank, int64_t timestamp); 211 void handleRd( unsigned bank, int64_t timestamp); 212 void handleWr( unsigned bank, int64_t timestamp); 213 void handleRef( unsigned bank, int64_t timestamp); 214 void handleRefB(unsigned bank, int64_ [all...] |
H A D | CmdHandlers.cc | 57 void CommandAnalysis::handleAct(unsigned bank, int64_t timestamp) argument 59 printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::ACT, timestamp, bank); 60 // If command is ACT - update number of acts, bank state of the 61 // target bank, first and latest activation cycle and the memory 63 // If the bank is already active ignore the command and generate a 65 if (isPrecharged(bank)) { 66 numberofactsBanks[bank]++; 76 bank_state[bank] = BANK_ACTIVE; 79 printWarning("Bank is already active!", MemCommand::ACT, timestamp, bank); 83 void CommandAnalysis::handleRd(unsigned bank, int64_ argument 96 handleWr(unsigned bank, int64_t timestamp) argument 109 handleRef(unsigned bank, int64_t timestamp) argument 134 handleRefB(unsigned bank, int64_t timestamp) argument 152 handlePre(unsigned bank, int64_t timestamp) argument 186 handlePreA(unsigned bank, int64_t timestamp) argument 226 handlePdnFAct(unsigned bank, int64_t timestamp) argument 247 handlePdnSAct(unsigned bank, int64_t timestamp) argument 268 handlePdnFPre(unsigned bank, int64_t timestamp) argument 282 handlePdnSPre(unsigned bank, int64_t timestamp) argument 353 handleSREn(unsigned bank, int64_t timestamp) argument 369 handleSREx(unsigned bank, int64_t timestamp) argument [all...] |
H A D | CommandAnalysis.cc | 165 // Reads through the trace file, identifies the timestamp, command and bank 216 // for each command identify timestamp, type and bank 220 // For command bank 221 unsigned bank = cmd.getBank(); local 226 handleAct(bank, timestamp); 228 handleRd(bank, timestamp); 230 handleWr(bank, timestamp); 232 handleRef(bank, timestamp); 234 handleRefB(bank, timestamp); 236 handlePre(bank, timestam [all...] |
H A D | MemCommand.h | 54 * 4. PRE - Explicit Precharge per bank 56 * 6 REFB- Refresh a particular bank 100 unsigned bank = 0, 111 void setBank(unsigned bank); 186 unsigned bank; member in class:Data::MemCommand
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H A D | MemCommand.cc | 49 unsigned bank, int64_t timestamp) : 51 bank(bank), 68 bank = _bank; 73 return bank; 48 MemCommand(MemCommand::cmds type, unsigned bank, int64_t timestamp) argument
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H A D | TraceParser.cc | 68 stringstream bank(item); 69 bank >> item_val;
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H A D | CmdScheduler.cc | 105 cmd.bank = static_cast<unsigned>(i); 126 transFinish.bank = 0; 128 PreRDWR.bank = -1; 236 b = PhysicalAddress.bankAddr; // the bank pointer per group. 240 endTime = max(transFinish.time, PRE[static_cast<size_t>(transFinish.bank)].time + 256 cmd.bank = 0; 258 cmd.time = max(max(max(transFinish.time, PRE[static_cast<size_t>(transFinish.bank)].time + memTimingSpec.RP), tREF), startTime); 287 // update to the current bank group address. 301 cmd.bank = bankAddr; 302 cmd.PhysicalAddr.bankAddr = cmd.bank; [all...] |
/gem5/src/cpu/pred/ |
H A D | tage_sc_l.cc | 180 TAGE_SC_L_TAGE::gindex(ThreadID tid, Addr pc, int bank) const 183 int hlen = (histLengths[bank] > pathHistBits) ? pathHistBits : 184 histLengths[bank]; 189 (shortPc >> ((int) abs(logTagTableSizes[bank] - bank) + 1)) ^ 190 threadHistory[tid].computeIndices[bank].comp ^ 191 F(threadHistory[tid].pathHist, hlen, bank); 193 index = gindex_ext(index, bank); 195 return (index & ((ULL(1) << (logTagTableSizes[bank])) - 1)); 199 TAGE_SC_L_TAGE::F(int a, int size, int bank) cons [all...] |
H A D | tage_sc_l_8KB.cc | 164 TAGE_SC_L_TAGE_8KB::gindex_ext(int index, int bank) const 166 return (index ^ (index >> logTagTableSizes[bank]) 167 ^ (index >> 2 * logTagTableSizes[bank])); 171 TAGE_SC_L_TAGE_8KB::gtag(ThreadID tid, Addr pc, int bank) const 173 int tag = (threadHistory[tid].computeIndices[bank - 1].comp << 2) ^ pc ^ 175 threadHistory[tid].computeIndices[bank].comp; 176 int hlen = (histLengths[bank] > pathHistBits) ? pathHistBits : 177 histLengths[bank]; 180 F(threadHistory[tid].pathHist, hlen, bank); 181 tag ^= threadHistory[tid].computeTags[0][bank] [all...] |
H A D | tage_sc_l_8KB.hh | 57 int gindex_ext(int index, int bank) const override; 59 uint16_t gtag(ThreadID tid, Addr pc, int bank) const override;
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H A D | tage_sc_l.hh | 105 int gindex(ThreadID tid, Addr pc, int bank) const override; 106 virtual int gindex_ext(int index, int bank) const = 0; 107 int F(int phist, int size, int bank) const override; 109 virtual uint16_t gtag(ThreadID tid, Addr pc, int bank) const override = 0;
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H A D | tage_sc_l_64KB.hh | 58 int gindex_ext(int index, int bank) const override; 60 uint16_t gtag(ThreadID tid, Addr pc, int bank) const override;
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H A D | tage_base.cc | 208 TAGEBase::F(int A, int size, int bank) const 213 A1 = (A & ((ULL(1) << logTagTableSizes[bank]) - 1)); 214 A2 = (A >> logTagTableSizes[bank]); 215 A2 = ((A2 << bank) & ((ULL(1) << logTagTableSizes[bank]) - 1)) 216 + (A2 >> (logTagTableSizes[bank] - bank)); 218 A = ((A << bank) & ((ULL(1) << logTagTableSizes[bank]) - 1)) 219 + (A >> (logTagTableSizes[bank] [all...] |
H A D | tage_sc_l_64KB.cc | 200 TAGE_SC_L_TAGE_64KB::gindex_ext(int index, int bank) const 206 TAGE_SC_L_TAGE_64KB::gtag(ThreadID tid, Addr pc, int bank) const 209 int tag = pc ^ threadHistory[tid].computeTags[0][bank].comp ^ 210 (threadHistory[tid].computeTags[1][bank].comp << 1); 212 return (tag & ((ULL(1) << tagTableTagWidths[bank]) - 1));
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/gem5/ext/drampower/src/libdrampower/ |
H A D | LibDRAMPower.cc | 68 void libDRAMPower::doCommand(MemCommand::cmds type, int bank, int64_t timestamp) argument 70 MemCommand cmd(type, static_cast<unsigned>(bank), timestamp);
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H A D | LibDRAMPower.h | 61 int bank,
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/gem5/src/mem/ |
H A D | dram_ctrl.cc | 124 // determine the rows per bank by looking at the total capacity 151 // basic bank group architecture checks -> 153 // must have at least one bank per bank group 159 // must have same number of banks in each bank group 161 fatal("Banks per rank (%d) must be evenly divisible by bank groups " 162 "per rank (%d) for equal banks per bank group\n", 168 "bank groups per rank (%d) is greater than 1\n", 174 "bank groups per rank (%d) is greater than 1\n", 177 // tRRD_L is greater than minimal, same bank grou 313 uint8_t bank; local [all...] |
H A D | dram_ctrl.hh | 152 uint8_t bank; member in struct:DRAMCtrl::Command 157 : type(_type), bank(_bank), timeStamp(time_stamp) 162 * A basic class to track the bank state, i.e. what row is 163 * currently open (if any), when is the bank free to accept a new 167 * The bank also keeps track of how many bytes have been accessed 178 uint8_t bank; member in class:DRAMCtrl::Bank 190 openRow(NO_ROW), bank(0), bankgr(0), 477 * @param Return true if the rank is idle from a bank 544 * and update bank timing parameters 654 const uint8_t bank; member in class:DRAMCtrl::DRAMPacket [all...] |
/gem5/src/gpu-compute/ |
H A D | lds_state.cc | 94 * derive the gpu mem packet from the packet and then count the bank conflicts 114 // Count the total number of bank conflicts for the local memory packet 120 std::vector<int> bank; local 125 // number of bank conflicts 132 bank.clear(); 133 bank.resize(banks, 0); 156 // calculate bank conflicts 160 bank[bankId]++; 161 max_bank = std::max(max_bank, bank[bankId]); 165 // the same bank (ban [all...] |