| /gem5/src/mem/cache/ |
| H A D | queue_entry.hh | 97 * @param _pkt The pending request packet.
101 Target(PacketPtr _pkt, Tick ready_time, Counter _order) argument
103 pkt(_pkt)
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| H A D | mshr.hh | 158 Target(PacketPtr _pkt, Tick _readyTime, Counter _order, argument
160 : QueueEntry::Target(_pkt, _readyTime, _order), source(_source),
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| /gem5/src/mem/ruby/slicc_interface/ |
| H A D | RubyRequest.hh | 67 PacketPtr _pkt, PrefetchBit _pb = PrefetchBit_No,
79 m_pkt(_pkt),
89 RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb,
103 m_pkt(_pkt),
116 RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb,
131 m_pkt(_pkt),
65 RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb = PrefetchBit_No, ContextID _proc_id = 100, ContextID _core_id = 99, HSAScope _scope = HSAScope_UNSPECIFIED, HSASegment _segment = HSASegment_GLOBAL) argument
87 RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb, unsigned _proc_id, unsigned _core_id, int _wm_size, std::vector<bool> & _wm_mask, DataBlock & _Data, HSAScope _scope = HSAScope_UNSPECIFIED, HSASegment _segment = HSASegment_GLOBAL) argument
114 RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb, unsigned _proc_id, unsigned _core_id, int _wm_size, std::vector<bool> & _wm_mask, DataBlock & _Data, std::vector< std::pair<int,AtomicOpFunctor*> > _atomicOps, HSAScope _scope = HSAScope_UNSPECIFIED, HSASegment _segment = HSASegment_GLOBAL) argument
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| /gem5/src/mem/ |
| H A D | simple_mem.hh | 81 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) argument
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| H A D | bridge.hh | 90 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) argument
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| H A D | serial_link.hh | 86 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) argument
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| H A D | dram_ctrl.hh | 734 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, argument
737 : entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
741 bankRef(bank_ref), rankRef(rank_ref), _qosValue(_pkt->qosValue())
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| /gem5/src/mem/ruby/system/ |
| H A D | Sequencer.hh | 49 SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, argument
51 : pkt(_pkt), m_type(_m_type), issue_time(_issue_time)
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| H A D | GPUCoalescer.hh | 70 GPUCoalescerRequest(PacketPtr _pkt, RubyRequestType _m_type, argument
72 : pkt(_pkt), m_type(_m_type), issue_time(_issue_time)
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| /gem5/src/cpu/simple/ |
| H A D | timing.hh | 180 void schedule(PacketPtr _pkt, Tick t);
332 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
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| H A D | timing.cc | 73 TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) argument
75 pkt = _pkt;
1047 TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
1049 : pkt(_pkt), cpu(_cpu)
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| /gem5/src/gpu-compute/ |
| H A D | gpu_tlb.hh | 395 PacketPtr _pkt);
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| H A D | gpu_tlb.cc | 1114 PacketPtr _pkt)
1116 outcome(tlb_outcome), pkt(_pkt)
1113 TLBEvent(GpuTLB* _tlb, Addr _addr, tlbOutcome tlb_outcome, PacketPtr _pkt) argument
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| /gem5/src/cpu/o3/ |
| H A D | lsq_unit_impl.hh | 65 PacketPtr _pkt, LSQUnit *lsq_ptr)
67 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
64 WritebackEvent(const DynInstPtr &_inst, PacketPtr _pkt, LSQUnit *lsq_ptr) argument
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