| /gem5/src/dev/x86/ |
| H A D | intdev.hh | 64 IntSlavePort(const std::string& _name, SimObject* _parent, argument
66 SimpleTimingPort(_name, _parent), device(dev)
99 IntMasterPort(const std::string& _name, SimObject* _parent, argument
101 QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
102 reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
|
| H A D | i8254.hh | 58 X86Intel8254Timer(const std::string &name, I8254 * _parent) : argument
59 Intel8254Timer(_parent, name), parent(_parent)
|
| /gem5/src/mem/probes/ |
| H A D | base.hh | 80 PacketListener(BaseMemProbe &_parent, argument
83 parent(_parent) {}
|
| /gem5/src/dev/virtio/ |
| H A D | console.hh | 111 TermRecvQueue(PortProxy &proxy, uint16_t size, VirtIOConsole &_parent) argument
112 : VirtQueue(proxy, size), parent(_parent) {}
135 TermTransQueue(PortProxy &proxy, uint16_t size, VirtIOConsole &_parent) argument
136 : VirtQueue(proxy, size), parent(_parent) {}
|
| H A D | fs9p.hh | 150 FSQueue(PortProxy &proxy, uint16_t size, VirtIO9PBase &_parent) argument
151 : VirtQueue(proxy, size), parent(_parent) {}
315 DiodDataEvent(VirtIO9PDiod &_parent, int fd, int event) argument
316 : PollEvent(fd, event), parent(_parent) {}
368 SocketDataEvent(VirtIO9PSocket &_parent, int fd, int event) argument
369 : PollEvent(fd, event), parent(_parent) {}
|
| H A D | block.hh | 166 RequestQueue(PortProxy &proxy, uint16_t size, VirtIOBlock &_parent) argument
167 : VirtQueue(proxy, size), parent(_parent) {}
|
| /gem5/src/mem/ |
| H A D | mem_delay.cc | 82 MemDelay::MasterPort::MasterPort(const std::string &_name, MemDelay &_parent) argument
83 : QueuedMasterPort(_name, &_parent,
84 _parent.reqQueue, _parent.snoopRespQueue),
85 parent(_parent)
124 MemDelay::SlavePort::SlavePort(const std::string &_name, MemDelay &_parent) argument
125 : QueuedSlavePort(_name, &_parent, _parent.respQueue),
126 parent(_parent)
|
| H A D | mem_delay.hh | 79 MasterPort(const std::string &_name, MemDelay &_parent);
105 SlavePort(const std::string &_name, MemDelay &_parent);
|
| /gem5/src/dev/ |
| H A D | mc146818.hh | 57 RTCEvent(MC146818 * _parent, Tick i);
75 RTCTickEvent(MC146818 * _parent) : argument
76 parent(_parent), offset(SimClock::Int::s)
|
| H A D | mc146818.cc | 312 MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i) argument
313 : parent(_parent), interval(i), offset(i)
|
| H A D | pixelpump.cc | 300 const char *name, BasePixelPump *_parent, CallbackType _func)
302 _name(name), parent(*_parent), func(_func),
299 PixelEvent( const char *name, BasePixelPump *_parent, CallbackType _func) argument
|
| /gem5/src/cpu/ |
| H A D | nativetrace.hh | 56 NativeTraceRecord(NativeTrace * _parent, argument
61 parent(_parent)
|
| /gem5/src/mem/cache/prefetch/ |
| H A D | pif.hh | 163 PrefetchListenerPC(PIFPrefetcher &_parent, ProbeManager *pm, argument
166 parent(_parent) {}
|
| H A D | base.hh | 72 PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm, argument
76 parent(_parent), isFill(_isFill), miss(_miss) {}
|
| /gem5/src/arch/arm/tracers/ |
| H A D | tarmac_parser.hh | 95 TarmacParserRecordEvent(TarmacParser& _parent, argument
101 parent(_parent), thread(_thread), inst(_inst), pc(_pc),
137 TarmacParser& _parent,
|
| H A D | tarmac_record_v8.hh | 134 TarmacTracer& _parent,
137 _parent, _macroStaticInst)
132 TarmacTracerRecordV8(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, ArmISA::PCState _pc, TarmacTracer& _parent, const StaticInstPtr _macroStaticInst = NULL) argument
|
| /gem5/src/sim/power/ |
| H A D | ThermalModel.py | 133 self._parent.thermal_components.append(cap)
139 self._parent.thermal_components.append(res)
145 self._parent.thermal_components.append(ref)
157 self._parent.thermal_components.append(node)
|
| /gem5/src/arch/arm/ |
| H A D | stage2_mmu.cc | 111 Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent, argument
113 : data(_data), numBytes(0), event(_event), parent(_parent), oVAddr(_oVAddr),
|
| H A D | semihosting.hh | 118 FileBase(ArmSemihosting &_parent, const char *name, const char *_mode) argument
119 : parent(_parent), _name(name), mode(_mode) {}
209 FileFeatures(ArmSemihosting &_parent,
225 File(ArmSemihosting &_parent, const char *name, const char *mode);
|
| H A D | stage2_mmu.hh | 83 Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
|
| /gem5/src/dev/arm/ |
| H A D | timer_cpulocal.hh | 137 CpuLocalTimer* _parent,
|
| H A D | generic_timer.hh | 126 SimObject &_parent; member in class:ArchTimer
286 GenericTimerISA(GenericTimer &_parent, unsigned _cpu) argument
287 : parent(_parent), cpu(_cpu) {}
|
| H A D | timer_sp804.cc | 57 Sp804::Timer::Timer(std::string __name, Sp804 *_parent, int int_num, Tick _clock) argument
58 : _name(__name), parent(_parent), intNum(int_num), clock(_clock), control(0x20),
|
| /gem5/src/python/m5/util/ |
| H A D | dot_writer.py | 242 if simNode._parent:
243 parent_type = get_node_type(simNode._parent)
253 parent = simNode._parent
257 parent = parent._parent
|
| /gem5/src/python/m5/ |
| H A D | SimObject.py | 1192 self._parent = None
1236 if self._parent:
1239 % (self, self._parent))
1344 assert self._parent is old_parent
1345 self._parent = None
1349 self._parent = parent
1356 return self._parent
1364 return self._parent is not None
1406 if not self._parent:
1408 elif isinstance(self._parent, MetaSimObjec
[all...] |