| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | dram_rot_gen.cc | 129 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
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| H A D | linear_gen.cc | 76 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
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| H A D | random_gen.cc | 82 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
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| H A D | dram_gen.cc | 141 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
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| /gem5/src/cpu/testers/directedtest/ |
| H A D | SeriesRequestGenerator.cc | 68 cmd = MemCmd::WriteReq;
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| H A D | InvalidateGenerator.cc | 75 cmd = MemCmd::WriteReq;
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| /gem5/ext/sst/ |
| H A D | ExtSlave.cc | 88 assert(pktCmd == ::MemCmd::WriteReq);
109 case ::MemCmd::WriteReq: cmd = GetX; break;
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| H A D | ExtMaster.cc | 138 case GetX: cmdO = MemCmd::WriteReq; data = true; break;
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| /gem5/src/mem/ |
| H A D | port_proxy.cc | 71 Packet pkt(req, MemCmd::WriteReq);
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| H A D | packet.hh | 91 WriteReq, enumerator in enum:MemCmd::Command
563 return (cmd == MemCmd::WriteReq || cmd == MemCmd::WriteLineReq) &&
778 cmd = MemCmd::WriteReq;
907 return MemCmd::WriteReq;
1327 return (cmd == MemCmd::WriteReq && !req->getByteEnable().empty());
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| /gem5/src/gpu-compute/ |
| H A D | shader.cc | 240 } else if (cmd == MemCmd::WriteReq) {
367 AccessMem(address, ptr, size, cu_id, MemCmd::WriteReq, false);
374 AccessMem(address, ptr, size, cu_id, MemCmd::WriteReq,
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| H A D | dispatcher.cc | 364 shader->AccessMem(addr, &val, sizeof(int), 0, MemCmd::WriteReq, true);
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| /gem5/src/dev/ |
| H A D | dma_device.hh | 182 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data,
189 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
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| /gem5/src/mem/ruby/system/ |
| H A D | CacheRecorder.cc | 130 requestType = MemCmd::WriteReq;
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| /gem5/src/dev/arm/ |
| H A D | smmu_v3_proc.cc | 117 a.pkt = new Packet(req, MemCmd::WriteReq);
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| H A D | ufs_device.cc | 2100 dmaPort.dmaAction(MemCmd::WriteReq, start, size,
2108 dmaPort.dmaAction(MemCmd::WriteReq, start, size,
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| /gem5/src/cpu/testers/rubytest/ |
| H A D | Check.cc | 105 cmd = MemCmd::WriteReq;
191 cmd = MemCmd::WriteReq;
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| /gem5/src/cpu/testers/memtest/ |
| H A D | memtest.cc | 284 pkt = new Packet(req, MemCmd::WriteReq);
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| /gem5/src/cpu/testers/garnet_synthetic_traffic/ |
| H A D | GarnetSyntheticTraffic.cc | 262 // following 3 types (randomly) : ReadReq, INST_FETCH, WriteReq
305 requestType = MemCmd::WriteReq;
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| /gem5/src/dev/pci/ |
| H A D | copy_engine.cc | 530 cePort.dmaAction(MemCmd::WriteReq, ce->pciToDma(curDmaDesc->dest),
599 cePort.dmaAction(MemCmd::WriteReq,
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| /gem5/util/tlm/src/ |
| H A D | sc_master_port.cc | 61 cmd = MemCmd::WriteReq;
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| /gem5/src/systemc/tlm_bridge/ |
| H A D | tlm_to_gem5.cc | 82 cmd = MemCmd::WriteReq;
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| /gem5/src/arch/x86/ |
| H A D | pagetable_walker.cc | 532 write->cmd = MemCmd::WriteReq;
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| /gem5/src/mem/cache/ |
| H A D | base.hh | 343 * It first determines whether a WriteReq MSHR should be delayed,
413 cmd == MemCmd::WriteReq ||
1383 * The number of times the allocator will delay an WriteReq MSHR.
1389 * WriteReq MSHR.
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| /gem5/src/cpu/kvm/ |
| H A D | base.cc | 1134 const MemCmd cmd(write ? MemCmd::WriteReq : MemCmd::ReadReq);
|