Searched refs:RAS (Results 1 - 11 of 11) sorted by relevance

/gem5/ext/drampower/src/
H A DMemTimingSpec.cc62 RAS(0),
99 RAS = getParamValWithDefault("RAS", 0);
H A DMemTimingSpec.h67 int64_t RAS; member in class:Data::MemTimingSpec
H A DMemoryPowerModel.cc189 energy.act_energy = vdd0Domain.calcTivEnergy(sum(c.numberofactsBanks) * t.RAS , mps.idd0 - mps.idd3n);
190 energy.pre_energy = vdd0Domain.calcTivEnergy(sum(c.numberofpresBanks) * (t.RC - t.RAS) , mps.idd0 - mps.idd2n);
214 int64_t tRefBlocal = (t.REFB == 0) ? (t.RAS + t.RP) : (t.REFB);
218 energy.act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofactsBanks[i] * t.RAS, mps.idd0 - ione);
292 energy.act_energy += vdd2Domain.calcTivEnergy(sum(c.numberofactsBanks) * t.RAS , mps.idd02 - mps.idd3n2);
293 energy.pre_energy += vdd2Domain.calcTivEnergy(sum(c.numberofpresBanks) * (t.RC - t.RAS) , mps.idd02 - mps.idd2n2);
H A DCommandAnalysis.cc187 activation_cycle[cmd.getBank()] + memSpec.memTimingSpec.RAS);
H A DCmdHandlers.cc146 actcyclesBanks[bank] += memSpec.memTimingSpec.RAS + memSpec.memTimingSpec.RP;
H A DCmdScheduler.cc401 static_cast<int>(memTimingSpec.RAS),
/gem5/src/cpu/pred/
H A Dbpred_unit.cc64 RAS(numThreads),
68 for (auto& r : RAS)
116 .desc("Number of times the RAS was used to get a target.")
121 .desc("Number of incorrect RAS predictions.")
176 // If so, get its target addr either from the BTB or the RAS.
177 // Save off record of branch stuff so the RAS can be fixed
217 // Now lookup in the BTB or RAS.
223 // in the RAS.
224 TheISA::PCState rasTop = RAS[tid].top();
227 // Record the top entry of the RAS, an
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H A Dbpred_unit.hh202 * information needed to update the predictor, BTB, and RAS.
233 /** The RAS target (only valid if a return). */
236 /** The RAS index of the instruction (only valid if a call). */
245 /** Whether or not the RAS was used. */
248 /* Whether or not the RAS was pushed */
286 std::vector<ReturnAddrStack> RAS; member in class:BPredUnit
305 /** Stat for number of times the RAS is used to get a target. */
307 /** Stat for number of times the RAS is incorrect. */
/gem5/ext/mcpat/
H A Dcore.cc287 L1_localBPT(NULL), L2_localBPT(NULL), chooser(NULL), RAS(NULL),
424 //RAS return address stacks are Duplicated for each thread.
445 RAS = new ArrayST(xml_data, &interface_ip, "RAS", Core_device, clockRate,
447 RAS->output_data.area *= core_params.num_hthreads;
448 area.set_area(area.get_area() + RAS->local_result.area *
2267 RAS->tdp_stats.reset();
2268 RAS->tdp_stats.readAc.access = tdp_read_accesses;
2269 RAS->tdp_stats.writeAc.access = 0;
2270 RAS
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H A Dcore.h68 ArrayST* RAS; member in class:BranchPredictor
/gem5/src/mem/
H A Ddrampower.cc85 timingSpec.RAS = divCeil(p->tRAS, p->tCK);

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