| /gem5/src/mem/ |
| H A D | hmc_controller.hh | 85 virtual void recvRangeChange(PortID master_port_id);
90 virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
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| H A D | noncoherent_xbar.hh | 100 NoncoherentXBar &_xbar, PortID _id)
153 NoncoherentXBar &_xbar, PortID _id)
178 virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
179 virtual bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
180 void recvReqRetry(PortID master_port_id);
181 Tick recvAtomicBackdoor(PacketPtr pkt, PortID slave_port_id,
183 void recvFunctional(PacketPtr pkt, PortID slave_port_id);
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| H A D | coherent_xbar.hh | 104 CoherentXBar &_xbar, PortID _id)
163 CoherentXBar &_xbar, PortID _id)
302 bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
303 bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
304 void recvTimingSnoopReq(PacketPtr pkt, PortID master_port_id);
305 bool recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id);
306 void recvReqRetry(PortID master_port_id);
317 forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id)
331 void forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id,
334 Tick recvAtomicBackdoor(PacketPtr pkt, PortID slave_port_i
[all...] |
| H A D | xbar.hh | 320 AddrRangeMap<PortID, 3> portMap;
328 std::unordered_map<RequestPtr, PortID> routeTo;
341 virtual void recvRangeChange(PortID master_port_id);
350 PortID findPort(AddrRange addr_range);
384 PortID defaultPortID;
413 PortID idx=InvalidPortID) override;
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| H A D | hmc_controller.cc | 22 void HMCController::recvRangeChange(PortID master_port_id)
42 bool HMCController::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
52 PortID master_port_id = rotate_counter();
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| H A D | noncoherent_xbar.cc | 102 NoncoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
111 PortID master_port_id = findPort(pkt->getAddrRange());
180 NoncoherentXBar::recvTimingResp(PacketPtr pkt, PortID master_port_id)
188 const PortID slave_port_id = route_lookup->second;
237 NoncoherentXBar::recvReqRetry(PortID master_port_id)
246 NoncoherentXBar::recvAtomicBackdoor(PacketPtr pkt, PortID slave_port_id,
257 PortID master_port_id = findPort(pkt->getAddrRange());
286 NoncoherentXBar::recvFunctional(PacketPtr pkt, PortID slave_port_id)
309 PortID dest_id = findPort(pkt->getAddrRange());
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| H A D | qport.hh | 80 RespPacketQueue &resp_queue, PortID id = InvalidPortID) :
135 PortID id = InvalidPortID) :
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| H A D | port.cc | 57 MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id)
114 SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id)
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| H A D | external_master.hh | 126 PortID idx=InvalidPortID) override;
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| H A D | external_slave.hh | 132 PortID idx=InvalidPortID) override;
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| H A D | coherent_xbar.cc | 143 CoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
156 PortID master_port_id = findPort(pkt->getAddrRange());
365 PortID rsp_port_id = slave_port_id;
440 CoherentXBar::recvTimingResp(PacketPtr pkt, PortID master_port_id)
448 const PortID slave_port_id = route_lookup->second;
502 CoherentXBar::recvTimingSnoopReq(PacketPtr pkt, PortID master_port_id)
562 CoherentXBar::recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id)
570 const PortID dest_port_id = route_lookup->second;
688 CoherentXBar::forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id,
716 CoherentXBar::recvReqRetry(PortID master_port_i
[all...] |
| /gem5/src/sim/ |
| H A D | port.cc | 52 Port::Port(const std::string& _name, PortID _id) :
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| H A D | port.hh | 74 const PortID id;
93 Port(const std::string& _name, PortID _id);
109 PortID getId() const { return id; }
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| /gem5/src/dev/ |
| H A D | intpin.hh | 47 IntSinkPinBase(const std::string &_name, PortID _id, int num) :
86 IntSinkPin(const std::string &_name, PortID _id, Device *dev, int num) :
88 IntSinkPin(const std::string &_name, PortID _id, Device *dev) :
99 IntSourcePinBase(const std::string &_name, PortID _id, bool def_state) :
114 IntSourcePin(const std::string &_name, PortID _id, Device *owner,
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| H A D | io_device.cc | 67 PioDevice::getPort(const std::string &if_name, PortID idx)
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| /gem5/src/cpu/testers/rubytest/ |
| H A D | RubyTester.hh | 65 PortID globalIdx;
74 CpuPort(const std::string &_name, RubyTester *_tester, PortID _id,
75 PortID _index)
99 PortID idx=InvalidPortID) override;
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| /gem5/src/systemc/ |
| H A D | sc_port_wrapper.hh | 59 ScPortWrapper(ScPort& p, const std::string& name, PortID id)
99 ScInterfaceWrapper(IF& i, const std::string name, PortID id)
140 ScExportWrapper(ScExport& p, const std::string& name, PortID id)
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| H A D | tlm_port_wrapper.hh | 61 InitiatorSocket &i, const std::string &_name, PortID _id) :
97 PortID _id) :
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| /gem5/src/dev/net/ |
| H A D | etherbus.hh | 75 PortID idx=InvalidPortID) override;
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| H A D | etherbus.cc | 85 EtherBus::getPort(const std::string &if_name, PortID idx)
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| /gem5/src/cpu/testers/directedtest/ |
| H A D | RubyDirectedTester.hh | 57 PortID _id)
72 PortID idx=InvalidPortID) override;
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| /gem5/src/mem/ruby/system/ |
| H A D | RubyPort.hh | 85 PortID id, bool _no_retry_on_stall);
152 PortID idx=InvalidPortID) override;
183 bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
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| /gem5/src/dev/arm/ |
| H A D | smmu_v3.hh | 176 Tick slaveRecvAtomic(PacketPtr pkt, PortID id);
177 bool slaveRecvTimingReq(PacketPtr pkt, PortID id);
192 PortID id = InvalidPortID) override;
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| /gem5/src/gpu-compute/ |
| H A D | tlb_coalescer.hh | 159 PortID _index)
186 PortID _index)
215 PortID idx=InvalidPortID) override;
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| /gem5/src/base/ |
| H A D | types.hh | 237 typedef int16_t PortID; typedef
238 const PortID InvalidPortID = (PortID)-1;
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