Searched refs:PMU (Results 1 - 6 of 6) sorted by relevance
| /gem5/src/sim/probe/ |
| H A D | pmu.hh | 49 * PMU probe point
51 * This probe point provides a unified interface for PMU
52 * instrumentation of SimObjects. SimObjects that need PMU
56 typedef ProbePointArg<uint64_t> PMU; typedef in namespace:ProbePoints
57 typedef std::unique_ptr<PMU> PMUUPtr;
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| /gem5/src/arch/arm/ |
| H A D | pmu.cc | 57 const RegVal PMU::reg_pmcr_wr_mask = 0x39;
59 PMU::PMU(const ArmPMUParams *p) function in class:ArmISA::PMU
72 DPRINTF(PMUVerbose, "Initializing the PMU.\n");
75 fatal("The PMU can only accept 31 counters, %d counters requested.\n",
79 warn_if(!p->interrupt, "ARM PMU: No interrupt specified, interrupt " \
92 PMU::~PMU()
97 PMU::setThreadContext(ThreadContext *tc)
99 DPRINTF(PMUVerbose, "Assigning PMU t
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| H A D | pmu.hh | 67 * Model of an ARM PMU version 3
69 * This class implements a subset of the ARM PMU v3 specification as
71 * features of the PMU, however the following features are known to be
76 * <li>Access controls (the PMU currently ignores the execution level).
80 * The PMU itself does not implement any events, in merely provides an
89 * memory references synthesized from loads and stores), the PMU
91 * switches between CPU models that share the same PMU, PMU events for
92 * all of the CPU models can be registered with the PMU.
97 class PMU class in namespace:ArmISA
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| H A D | tlb.cc | 561 ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills"));
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| /gem5/src/cpu/pred/ |
| H A D | bpred_unit.cc | 150 ptr.reset(new ProbePoints::PMU(getProbeManager(), name));
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| /gem5/src/cpu/ |
| H A D | base.cc | 382 ptr.reset(new ProbePoints::PMU(getProbeManager(), name));
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