arch/arm/pmu.cc

57 const RegVal PMU::reg_pmcr_wr_mask = 0x39;
59 PMU::PMU(const ArmPMUParams *p)
72     DPRINTF(PMUVerbose, "Initializing the PMU.\n");
75         fatal("The PMU can only accept 31 counters, %d counters requested.\n",
79     warn_if(!p->interrupt, "ARM PMU: No interrupt specified, interrupt " \
92 PMU::~PMU()
97 PMU::setThreadContext(ThreadContext *tc)
99     DPRINTF(PMUVerbose, "Assigning PMU to ContextID %i.\n", tc->contextId());
107 PMU::addSoftwareIncrementEvent(unsigned int id)
110     DPRINTF(PMUVerbose, "PMU: Adding SW increment event with id '0x%x'\n", id);
129 PMU::addEventProbe(unsigned int id, SimObject *obj, const char *probe_name)
132     DPRINTF(PMUVerbose, "PMU: Adding Probe Driven event with id '0x%x'"
155 PMU::registerEvent(uint32_t id)
171 PMU::drainResume()
178 PMU::regProbeListeners()
194 PMU::setMiscReg(int misc_reg, RegVal val)
295         panic("Unexpected PMU register: %i\n", miscRegName[misc_reg]);
303 PMU::readMiscReg(int misc_reg)
312 PMU::readMiscRegInt(int misc_reg)
393         panic("Unexpected PMU register: %i\n", miscRegName[misc_reg]);
402 PMU::setControlReg(PMCR_t val)
407         DPRINTF(PMUVerbose, "PMU reset all events to zero.\n");
412         DPRINTF(PMUVerbose, "PMU reset cycle counter to zero.\n");
425 PMU::updateAllCounters()
446 PMU::PMUEvent::attachEvent(PMU::CounterState *user)
456 PMU::PMUEvent::increment(const uint64_t val)
464 PMU::PMUEvent::detachEvent(PMU::CounterState *user)
474 PMU::RegularEvent::RegularProbe::notify(const uint64_t &val)
480 PMU::RegularEvent::enable()
489 PMU::RegularEvent::disable()
495 PMU::CounterState::isFiltered() const
519         panic("Unexpected execution level in PMU::isFiltered.\n");
524 PMU::CounterState::detach()
536 PMU::CounterState::attach(PMUEvent* event)
547 PMU::CounterState::getValue() const
559 PMU::CounterState::setValue(uint64_t val)
573 PMU::updateCounter(CounterState &ctr)
586             warn("Can't enable PMU counter of type '0x%x': "
596 PMU::resetEventCounts()
603 PMU::setCounterValue(CounterId id, uint64_t val)
615 PMU::PMEVTYPER_t
616 PMU::getCounterTypeRegister(CounterId id) const
630 PMU::setCounterTypeRegister(CounterId id, PMEVTYPER_t val)
654 PMU::setOverflowStatus(RegVal new_val)
668 PMU::raiseInterrupt()
671         DPRINTF(PMUVerbose, "Delivering PMU interrupt.\n");
674         warn_once("Dropping PMU interrupt as no interrupt has "
680 PMU::clearInterrupt()
683         DPRINTF(PMUVerbose, "Clearing PMU interrupt.\n");
686         warn_once("Dropping PMU interrupt as no interrupt has "
692 PMU::serialize(CheckpointOut &cp) const
694     DPRINTF(Checkpoint, "Serializing Arm PMU\n");
712 PMU::unserialize(CheckpointIn &cp)
714     DPRINTF(Checkpoint, "Unserializing Arm PMU\n");
739 PMU::PMUEvent*
740 PMU::getEvent(uint64_t eventId)
753 PMU::CounterState::serialize(CheckpointOut &cp) const
761 PMU::CounterState::unserialize(CheckpointIn &cp)
769 PMU::CounterState::add(uint64_t delta)
794         // Deliver a PMU interrupt if interrupt delivery is enabled
805 PMU::SWIncrementEvent::write(uint64_t val)
816 ArmISA::PMU *
819     return new ArmISA::PMU(this);