Searched refs:NUM_MEM_CMDS (Results 1 - 4 of 4) sorted by relevance

/gem5/src/mem/cache/
H A Dbase.hh923 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
931 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
941 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
948 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
955 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
962 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
983 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
990 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
997 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
1002 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
[all...]
H A Dbase.cc1884 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1931 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1967 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2003 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2040 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2077 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2158 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2194 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2230 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2267 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS;
[all...]
/gem5/src/mem/
H A Dxbar.cc529 .init(MemCmd::NUM_MEM_CMDS)
535 for (int i = 0; i < MemCmd::NUM_MEM_CMDS; i++) {
H A Dpacket.hh139 NUM_MEM_CMDS enumerator in enum:MemCmd::Command

Completed in 22 milliseconds