Searched refs:MISCREG_TLBTR (Results 1 - 5 of 5) sorted by relevance

/gem5/src/arch/arm/
H A Dutility.cc495 case MISCREG_TLBTR:
H A Dmiscregs.hh147 MISCREG_TLBTR, enumerator in enum:ArmISA::MiscRegIndex
H A Disa.cc147 miscRegs[MISCREG_TLBTR] = 1;
1090 case MISCREG_TLBTR:
H A Dmiscregs.cc146 return MISCREG_TLBTR;
3118 InitReg(MISCREG_TLBTR)
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc135 { "tlbtr", MISCREG_TLBTR },

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