Searched refs:GICD_SETSPI_SR (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/dev/arm/ | ||
| H A D | gic_v3_distributor.hh | 77 GICD_SETSPI_SR = 0x0050, enumerator in enum:Gicv3Distributor::__anon7 |
| H A D | gic_v3_distributor.cc | 956 case GICD_SETSPI_SR: { |
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