Searched refs:GICD_ITARGETSR (Results 1 - 5 of 5) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_distributor.hh117 static const AddrRange GICD_ITARGETSR; // GICv2 legacy member in class:Gicv3Distributor
H A Dgic_v2.cc62 const AddrRange GicV2::GICD_ITARGETSR (0x800, 0xbff);
236 if (GICD_ITARGETSR.contains(daddr)) {
237 Addr int_num = daddr - GICD_ITARGETSR.start();
506 if (GICD_ITARGETSR.contains(daddr)) {
507 Addr int_num = daddr - GICD_ITARGETSR.start();
H A Dgic_v2.hh90 static const AddrRange GICD_ITARGETSR; // processor target registers member in class:GicV2
296 /** GICD_ITARGETSR{8..255}
H A Dgic_v3_distributor.cc61 const AddrRange Gicv3Distributor::GICD_ITARGETSR (0x0800, 0x08ff);
327 } else if (GICD_ITARGETSR.contains(addr)) {
331 "GICD_ITARGETSR is RAZ/WI, legacy not supported!\n");
727 } else if (GICD_ITARGETSR.contains(addr)) {
731 "GICD_ITARGETSR is RAZ/WI, legacy not supported!\n");
/gem5/src/arch/arm/kvm/
H A Dgic.cc401 set = GicV2::GICD_ITARGETSR.start() + 32;

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