Searched refs:BaseTLB (Results 1 - 25 of 75) sorted by relevance

123

/gem5/src/arch/mips/
H A DMipsTLB.py35 from m5.objects.BaseTLB import BaseTLB
37 class MipsTLB(BaseTLB):
H A Dtlb.hh57 class TLB : public BaseTLB
90 void takeOverFrom(BaseTLB *otlb) override {}
/gem5/src/arch/power/
H A DPowerTLB.py34 from m5.objects.BaseTLB import BaseTLB
36 class PowerTLB(BaseTLB):
H A Dtlb.hh99 class TLB : public BaseTLB
136 void takeOverFrom(BaseTLB *otlb) override {}
/gem5/src/arch/riscv/
H A DRiscvTLB.py35 from m5.objects.BaseTLB import BaseTLB
37 class RiscvTLB(BaseTLB):
H A Dtlb.hh56 class TLB : public BaseTLB
89 void takeOverFrom(BaseTLB *otlb) override {}
/gem5/src/arch/sparc/
H A DSparcTLB.py32 from m5.objects.BaseTLB import BaseTLB
34 class SparcTLB(BaseTLB):
/gem5/src/arch/alpha/
H A DAlphaTLB.py32 from m5.objects.BaseTLB import BaseTLB
34 class AlphaTLB(BaseTLB):
H A Dtlb.hh53 class TLB : public BaseTLB
88 void takeOverFrom(BaseTLB *otlb) override {}
/gem5/src/arch/x86/
H A DX86TLB.py41 from m5.objects.BaseTLB import BaseTLB
53 class X86TLB(BaseTLB):
H A Dpagetable_walker.hh109 BaseTLB::Mode mode;
116 WalkerState(Walker * _walker, BaseTLB::Translation *_translation,
125 void initState(ThreadContext * _tc, BaseTLB::Mode _mode,
162 Fault start(ThreadContext * _tc, BaseTLB::Translation *translation,
163 const RequestPtr &req, BaseTLB::Mode mode);
165 unsigned &logBytes, BaseTLB::Mode mode);
H A Dvtophys.cc67 tc, addr, logBytes, BaseTLB::Read);
H A Dtlb.hh58 class TLB : public BaseTLB
72 void takeOverFrom(BaseTLB *otlb) override {}
/gem5/src/arch/generic/
H A DBaseTLB.py34 class BaseTLB(SimObject): class in inherits:SimObject
35 type = 'BaseTLB'
H A Dtlb.hh52 class BaseTLB : public SimObject class in inherits:SimObject
55 BaseTLB(const Params *p) : SimObject(p) {} function in class:BaseTLB
128 virtual void takeOverFrom(BaseTLB *otlb) = 0;
144 class GenericTLB : public BaseTLB
148 : BaseTLB(p)
/gem5/src/cpu/
H A Dtranslation.hh75 BaseTLB::Mode mode;
82 uint64_t *_res, BaseTLB::Mode _mode)
87 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
97 uint64_t *_res, BaseTLB::Mode _mode)
103 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
218 class DataTranslation : public BaseTLB::Translation
253 BaseTLB::Mode mode)
H A Dsimple_thread.cc77 Process *_process, BaseTLB *_itb,
78 BaseTLB *_dtb, TheISA::ISA *_isa)
88 BaseTLB *_itb, BaseTLB *_dtb,
/gem5/src/arch/arm/
H A Dstage2_lookup.hh58 class Stage2LookUp : public BaseTLB::Translation
66 BaseTLB::Mode mode;
78 TLB::Translation *_transState, BaseTLB::Mode _mode, bool _timing,
92 void mergeTe(const RequestPtr &req, BaseTLB::Mode mode);
101 BaseTLB::Mode mode);
H A Dstage2_mmu.hh70 class Stage2Translation : public BaseTLB::Translation
91 BaseTLB::Mode mode);
101 parent.stage2Tlb()->translateTiming(req, tc, this, BaseTLB::Read);
H A DArmTLB.py43 from m5.objects.BaseTLB import BaseTLB
63 class ArmTLB(BaseTLB):
H A Dvtophys.cc84 fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran);
89 fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran);
H A Dstage2_mmu.cc73 fault = stage2Tlb()->translateFunctional(req, tc, BaseTLB::Read);
75 fault = stage2Tlb()->translateAtomic(req, tc, BaseTLB::Read);
122 ThreadContext *tc, BaseTLB::Mode mode)
/gem5/src/mem/cache/prefetch/
H A Dqueued.hh57 struct DeferredPacket : public BaseTLB::Translation {
125 ThreadContext *tc, BaseTLB::Mode mode) override;
131 void startTranslation(BaseTLB *tlb);
H A Dbase.hh331 BaseTLB * tlb;
380 * Add a BaseTLB object to be used whenever a translation is needed.
383 * @param tlb pointer to the BaseTLB object to add
385 void addTLB(BaseTLB *tlb);
/gem5/src/gpu-compute/
H A Dshader.hh63 class BaseTLB;
196 void functionalTLBAccess(PacketPtr pkt, int cu_id, BaseTLB::Mode mode);

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