/gem5/src/systemc/tests/systemc/1666-2011-compliance/kill_reset/ |
H A D | kill_reset.cpp | 48 SC_THREAD(target); 84 // ticker process killed by target 137 void target() function in struct:M3 150 cout << "sc_unwind_exception caught by target" << endl;
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/gem5/src/systemc/tests/tlm/bugs/multi_passthrough_sockets_bug/ |
H A D | multi_passthrough_sockets_bug.cpp | 103 // Simple empty extension to verify the target module is receiving it 188 target_module target("target"); 191 initiator.initiator_socket(target.target_socket);
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/gem5/src/arch/ |
H A D | micro_asm.py | 69 def __init__(self, name, target): 71 self.target = target 74 return "%s: %s\n" % (self.name, self.target)
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/gem5/ext/systemc/src/sysc/kernel/ |
H A D | sc_phase_callback_registry.cpp | 69 { return e.target == ref_; } 248 sc_object::hierarchy_scope scope(it->target); 249 it->target->do_simulation_phase_callback();
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H A D | sc_phase_callback_registry.h | 63 cb_type* target; member in struct:sc_core::sc_phase_callback_registry::entry
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/gem5/src/systemc/tests/tlm/update_original/ |
H A D | update_original.cpp | 244 Target *target; local 251 target = new Target ("target"); 253 // One initiator is bound directly to one target with no intervening bus 255 // Bind initiator socket to target socket 257 interconnect ->init_socket.bind( target ->socket );
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/gem5/ext/testlib/ |
H A D | sandbox.py | 113 target=_log_output, 118 target=_log_output, 176 self.p = ExceptionProcess(target=self.entrypoint)
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/gem5/src/cpu/minor/ |
H A D | fetch2.cc | 155 branch.target, true, inst->id.threadId); 171 branch.target /* Not used */, false, inst->id.threadId); 178 /* Predicted taken, was taken but to a different target */ 179 DPRINTF(Branch, "Branch mis-predicted target inst: %s target: %s\n", 180 *inst, branch.target); 182 branch.target, true, inst->id.threadId); 210 branch.target = inst_pc; 232 DPRINTF(Branch, "Branch predicted taken inst: %s target: %s"
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H A D | execute.cc | 220 TheISA::PCState target = thread->pcState(); local 232 pc_before, target, (force_branch ? " (forcing)" : "")); 235 bool must_branch = pc_before != target || 244 TheISA::advancePC(target, inst->staticInst); 245 thread->pcState(target); 248 pc_before, target); 261 } else if (inst->predictedTarget == target) { 262 /* Branch prediction got the right target, kill the branch and 272 /* Branch prediction got the wrong target */ 274 " but got the wrong target (actua 295 updateBranchData( ThreadID tid, BranchData::Reason reason, MinorDynInstPtr inst, const TheISA::PCState &target, BranchData &branch) argument [all...] |
H A D | execute.hh | 224 MinorDynInstPtr inst, const TheISA::PCState &target,
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/gem5/ext/ply/example/BASIC/ |
H A D | basinterp.py | 142 def assign(self,target,value): 143 var, dim1, dim2 = target 236 target = instr[1] 238 self.assign(target,value) 242 for target in instr[1]: 245 self.assign(target,value)
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/gem5/src/cpu/kvm/ |
H A D | vm.hh | 426 * Ask the kernel for the preferred CPU target to simulate. 434 * @param[out] target Target structure to initialize. 436 void kvmArmPreferredTarget(struct kvm_vcpu_init &target) const;
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H A D | vm.cc | 567 KvmVM::kvmArmPreferredTarget(struct kvm_vcpu_init &target) const 569 if (ioctl(KVM_ARM_PREFERRED_TARGET, &target) == -1) { 570 panic("KVM: Failed to get ARM preferred CPU target (errno: %i)\n",
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/gem5/ext/pybind11/include/pybind11/ |
H A D | functional.h | 89 auto result = f_.template target<function_type>();
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/gem5/ext/systemc/src/sysc/datatypes/fx/ |
H A D | scfx_mant.h | 348 complement( scfx_mant& target, const scfx_mant& source, int size ) argument 352 target[i] = ~source[i];
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/gem5/src/systemc/ext/dt/fx/ |
H A D | scfx_mant.hh | 297 complement(scfx_mant &target, const scfx_mant &source, int size) argument 300 target[i] = ~source[i];
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/proc_ctrl/ |
H A D | proc_ctrl.cpp | 60 SC_THREAD(target);
194 void target()
function
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/gem5/src/dev/arm/ |
H A D | gic_v2.cc | 238 DPRINTF(GIC, "Reading processor target register for int# %#x \n", 788 and if current cpu is the target (for mp configs only) 867 uint8_t target = getCpuTarget(0, num); 869 num, target); 870 if ((target & (target - 1)) && !gem5ExtensionsEnabled) 874 getPendingInt(target, intNumToWord(num)) |= 1 << intNumToBit(num); 891 uint8_t target = getCpuTarget(0, num); 895 num, target); 897 getPendingInt(target, intNumToWor [all...] |
/gem5/src/mem/cache/ |
H A D | mshr.hh | 69 * needed to handle a cache miss including a list of target requests. 103 * possibly building a deferred target list and calling 147 * service and the target is not deferred, 148 * 2) when the MSHR becomes in service if the target is not 156 //!< target list allocate in the cache? 174 * target coming from another cache. 271 * @param order A counter giving a unique id to each target 319 * Track which bytes are written by requests in this target 374 * Deferred targets are promoted to the target list if they 376 * deferred target tha [all...] |
/gem5/src/cpu/pred/ |
H A D | tage_base.hh | 294 Addr target = MaxAddr); 306 * @param target The correct branch target 310 ThreadID tid, bool taken, BranchInfo *bi, Addr target); 319 * @param corrTarget The correct branch target
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/gem5/ext/pybind11/tests/ |
H A D | test_callbacks.py | 134 t = Thread(target=test_async_callbacks)
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/method_suspends_itself/ |
H A D | method_suspends_itself.cpp | 48 SC_METHOD(target); 336 void target() function in struct:Top
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/proc_ctrl_priority/ |
H A D | proc_ctrl_priority.cpp | 50 SC_THREAD(target); 299 void target() function in struct:Top
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/gem5/src/systemc/tests/tlm/multi_sockets/ |
H A D | MultiSocketSimpleSwitchAT.h | 35 may communicate in parallel as long as they do not talk to the same target. 37 If two masters address the same target at the same point of time, 44 many initiator talk to the same target. 56 target_socket_type target_socket; //the target multi socket 61 std::vector<std::deque<transaction_type*> > m_pendingReqs; //list of pending reqs per target 63 std::vector<sc_dt::uint64> m_masks; //address masks for each target 77 // complete on the target side 83 bool alreadyComplete; //has the txn already completed on the target side? 110 void bindTargetSocket(initiator_socket_type::base_target_socket_type& target 114 initiator_socket(target); //bin [all...] |
/gem5/src/systemc/core/ |
H A D | scheduler.cc | 228 listContains(ListNode *list, ListNode *target) argument 232 if (n == target)
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