Searched refs:setMiscReg (Results 51 - 62 of 62) sorted by relevance
123
/gem5/src/arch/arm/linux/ |
H A D | linux.hh | 65 ctc->setMiscReg(ArmISA::MISCREG_TPIDR_EL0, tls);
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H A D | process.cc | 152 tc->setMiscReg(MISCREG_TPIDRURO,tlsPtr); 163 tc->setMiscReg(MISCREG_TPIDRRO_EL0, tlsPtr);
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/gem5/src/arch/arm/kvm/ |
H A D | armv8_cpu.cc | 340 tc->setMiscReg(ri.idx, value);
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H A D | arm_cpu.cc | 743 tc->setMiscReg(MISCREG_CPSR, tc->readMiscRegNoEffect(MISCREG_CPSR)); 858 tc->setMiscReg(idx, getOneRegU64(id));
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/gem5/src/arch/arm/ |
H A D | isa.cc | 775 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 1619 pmu->setMiscReg(misc_reg, newVal); 2075 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 2080 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal);
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H A D | pmu.cc | 194 PMU::setMiscReg(int misc_reg, RegVal val) function in class:ArmISA::PMU 196 DPRINTF(PMUVerbose, "setMiscReg(%s, 0x%x)\n",
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H A D | utility.cc | 183 // setMiscReg "with effect" will set the misc register mapping correctly. 185 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
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H A D | isa.hh | 446 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
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/gem5/src/cpu/o3/ |
H A D | cpu.hh | 353 void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
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H A D | cpu.cc | 1191 FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) function in class:FullO3CPU 1194 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
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/gem5/src/arch/sparc/ |
H A D | isa.cc | 567 ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) function in class:SparcISA::ISA
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/gem5/src/arch/mips/ |
H A D | isa.cc | 476 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) function in class:MipsISA::ISA
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