Searched refs:setMiscReg (Results 51 - 62 of 62) sorted by relevance

123

/gem5/src/arch/arm/linux/
H A Dlinux.hh65 ctc->setMiscReg(ArmISA::MISCREG_TPIDR_EL0, tls);
H A Dprocess.cc152 tc->setMiscReg(MISCREG_TPIDRURO,tlsPtr);
163 tc->setMiscReg(MISCREG_TPIDRRO_EL0, tlsPtr);
/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc340 tc->setMiscReg(ri.idx, value);
H A Darm_cpu.cc743 tc->setMiscReg(MISCREG_CPSR, tc->readMiscRegNoEffect(MISCREG_CPSR));
858 tc->setMiscReg(idx, getOneRegU64(id));
/gem5/src/arch/arm/
H A Disa.cc775 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
1619 pmu->setMiscReg(misc_reg, newVal);
2075 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
2080 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal);
H A Dpmu.cc194 PMU::setMiscReg(int misc_reg, RegVal val) function in class:ArmISA::PMU
196 DPRINTF(PMUVerbose, "setMiscReg(%s, 0x%x)\n",
H A Dutility.cc183 // setMiscReg "with effect" will set the misc register mapping correctly.
185 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
H A Disa.hh446 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
/gem5/src/cpu/o3/
H A Dcpu.hh353 void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
H A Dcpu.cc1191 FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) function in class:FullO3CPU
1194 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
/gem5/src/arch/sparc/
H A Disa.cc567 ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) function in class:SparcISA::ISA
/gem5/src/arch/mips/
H A Disa.cc476 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) function in class:MipsISA::ISA

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