/gem5/src/dev/arm/ |
H A D | smmu_v3_transl.hh | 58 PacketPtr pkt; member in struct:SMMUTranslRequest 60 static SMMUTranslRequest fromPacket(PacketPtr pkt, bool ats = false);
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H A D | pl111.hh | 372 Tick read(PacketPtr pkt) override; 373 Tick write(PacketPtr pkt) override;
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H A D | hdlcd.hh | 107 Tick read(PacketPtr pkt) override; 108 Tick write(PacketPtr pkt) override;
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H A D | generic_timer.hh | 307 Tick read(PacketPtr pkt) override; 308 Tick write(PacketPtr pkt) override;
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/gem5/src/mem/ruby/slicc_interface/ |
H A D | RubyRequest.hh | 156 bool functionalRead(Packet *pkt); 157 bool functionalWrite(Packet *pkt);
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/gem5/src/arch/generic/ |
H A D | memhelpers.hh | 67 getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData) argument 69 mem = pkt->get<MemT>(TheISA::GuestByteOrder);
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/gem5/src/mem/ruby/network/garnet2.0/ |
H A D | InputUnit.hh | 148 uint32_t functionalWrite(Packet *pkt);
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H A D | flit.hh | 100 bool functionalWrite(Packet *pkt);
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H A D | GarnetNetwork.cc | 443 GarnetNetwork::functionalWrite(Packet *pkt) 448 num_functional_writes += m_routers[i]->functionalWrite(pkt); 452 num_functional_writes += m_nis[i]->functionalWrite(pkt); 456 num_functional_writes += m_networklinks[i]->functionalWrite(pkt);
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/gem5/src/cpu/testers/rubytest/ |
H A D | RubyTester.hh | 81 virtual bool recvTimingResp(PacketPtr pkt);
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/gem5/src/dev/virtio/ |
H A D | base.hh | 667 * @param pkt Read request packet. 670 virtual void readConfig(PacketPtr pkt, Addr cfgOffset); 682 * @param pkt Write request packet. 685 virtual void writeConfig(PacketPtr pkt, Addr cfgOffset); 710 * @param pkt Read request packet. 714 void readConfigBlob(PacketPtr pkt, Addr cfgOffset, const uint8_t *cfg); 719 * @param pkt Write request packet. 723 void writeConfigBlob(PacketPtr pkt, Addr cfgOffset, uint8_t *cfg);
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/gem5/src/dev/ |
H A D | dma_device.hh | 87 * @param pkt Response packet to handler 90 void handleResp(PacketPtr pkt, Tick delay = 0); 145 bool recvTimingResp(PacketPtr pkt) override; 148 void queueDma(PacketPtr pkt);
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/gem5/src/gpu-compute/ |
H A D | lds_state.hh | 164 recvTimingReq(PacketPtr pkt); 167 recvAtomic(PacketPtr pkt) argument 173 recvFunctional(PacketPtr pkt);
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/gem5/src/dev/net/ |
H A D | ns_gige.cc | 153 NSGigE::writeConfig(PacketPtr pkt) argument 155 int offset = pkt->getAddr() & PCI_CONFIG_SIZE; 157 PciDevice::writeConfig(pkt); 189 NSGigE::read(PacketPtr pkt) argument 194 Addr daddr = pkt->getAddr() & 0xfff; 196 daddr, pkt->getAddr(), pkt->getSize()); 204 return readConfig(pkt); 209 pkt->setLE<uint32_t>(0); 210 pkt 411 write(PacketPtr pkt) argument [all...] |
H A D | dist_iface.cc | 651 DistIface::packetOut(EthPacketPtr pkt, Tick send_delay) argument 661 header.dataPacketLength = pkt->length; 662 header.simLength = pkt->simLength; 665 sendPacket(header, pkt); 669 pkt->length, send_delay);
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/gem5/src/cpu/ |
H A D | base.cc | 293 BaseCPU::mwait(ThreadID tid, PacketPtr pkt) 302 assert(pkt->req->hasPaddr()); 303 monitor.pAddr = pkt->getAddr() & mask; 771 bool AddressMonitor::doMonitor(PacketPtr pkt) { 772 assert(pkt->req->hasPaddr()); 774 if (pAddr == pkt->getAddr()) { 776 pkt->getAddr());
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/gem5/src/cpu/o3/ |
H A D | fetch_impl.hh | 389 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) argument 391 ThreadID tid = cpu->contextToThread(pkt->req->contextId()); 399 pkt->req != memReq[tid]) { 401 delete pkt; 405 memcpy(fetchBuffer[tid], pkt->getConstPtr<uint8_t>(), fetchBufferSize); 424 pkt->req->setAccessLatency(); 425 cpu->ppInstAccessComplete->notify(pkt); 427 delete pkt; 1678 DefaultFetch<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) argument 1682 assert(pkt [all...] |
H A D | lsq_unit.hh | 265 void checkSnoop(PacketPtr pkt); 287 void completeDataAccess(PacketPtr pkt); 359 void writeback(const DynInstPtr &inst, PacketPtr pkt); 441 WritebackEvent(const DynInstPtr &_inst, PacketPtr pkt, 455 PacketPtr pkt; member in class:LSQUnit::WritebackEvent 466 * @param pkt Response packet from the memory sub-system 468 bool recvTimingResp(PacketPtr pkt);
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H A D | fetch.hh | 109 virtual bool recvTimingResp(PacketPtr pkt); 253 void processCacheCompletion(PacketPtr pkt);
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/gem5/src/mem/ruby/network/ |
H A D | MessageBuffer.cc | 441 MessageBuffer::functionalWrite(Packet *pkt) argument 449 if (msg->functionalWrite(pkt)) { 464 if (msg->functionalWrite(pkt)) {
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/gem5/src/arch/arm/kvm/ |
H A D | gic.cc | 219 MuxingKvmGic::read(PacketPtr pkt) argument 222 return GicV2::read(pkt); 228 MuxingKvmGic::write(PacketPtr pkt) argument 231 return GicV2::write(pkt);
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/gem5/src/mem/cache/tags/ |
H A D | base.hh | 312 * @param pkt Packet holding the address to update 315 virtual void insertBlock(const PacketPtr pkt, CacheBlk *blk);
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H A D | sector_tags.cc | 173 SectorTags::insertBlock(const PacketPtr pkt, CacheBlk *blk) 193 BaseTags::insertBlock(pkt, blk);
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/gem5/src/mem/ |
H A D | xbar.hh | 365 * @param pkt Packet to populate with timings 368 void calcPacketTiming(PacketPtr pkt, Tick header_delay);
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/gem5/src/cpu/kvm/ |
H A D | base.hh | 587 * Interface to send Atomic or Timing IO request. Assumes that the pkt 591 Tick submitIO(PacketPtr pkt); 606 bool recvTimingResp(PacketPtr pkt) override;
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