Searched refs:pkt (Results 276 - 300 of 375) sorted by relevance

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/gem5/src/dev/virtio/
H A Dbase.cc408 VirtIODeviceBase::readConfig(PacketPtr pkt, Addr cfgOffset) argument
414 VirtIODeviceBase::writeConfig(PacketPtr pkt, Addr cfgOffset) argument
420 VirtIODeviceBase::readConfigBlob(PacketPtr pkt, Addr cfgOffset, const uint8_t *cfg) argument
422 const unsigned size(pkt->getSize());
427 pkt->makeResponse();
428 pkt->setData(const_cast<uint8_t *>(cfg) + cfgOffset);
432 VirtIODeviceBase::writeConfigBlob(PacketPtr pkt, Addr cfgOffset, uint8_t *cfg) argument
434 const unsigned size(pkt->getSize());
439 pkt->makeResponse();
440 pkt
[all...]
/gem5/src/cpu/trace/
H A Dtrace_cpu.hh212 * @param pkt Pointer to packet received
214 void dcacheRecvTimingResp(PacketPtr pkt);
243 * @param pkt Pointer to packet received
246 bool recvTimingResp(PacketPtr pkt);
251 * @param pkt Pointer to packet received
253 void recvTimingSnoopReq(PacketPtr pkt) { } argument
284 * @param pkt Pointer to packet received
287 bool recvTimingResp(PacketPtr pkt);
292 * @param pkt Pointer to packet received
294 void recvTimingSnoopReq(PacketPtr pkt) argument
302 recvFunctionalSnoop(PacketPtr pkt) argument
[all...]
H A Dtrace_cpu.cc671 PacketPtr pkt; local
674 pkt = Packet::createRead(req);
676 pkt = Packet::createWrite(req);
679 pkt->dataDynamic(pkt_data);
682 bool success = port.sendTimingReq(pkt);
690 return pkt;
739 TraceCPU::ElasticDataGen::completeMemAccess(PacketPtr pkt) argument
742 if (pkt->isWrite()) {
752 auto graph_itr = depGraph.find(pkt->req->getReqInstSeqNum());
1161 PacketPtr pkt local
1217 recvTimingResp(PacketPtr pkt) argument
1233 dcacheRecvTimingResp(PacketPtr pkt) argument
1240 recvTimingResp(PacketPtr pkt) argument
[all...]
/gem5/src/cpu/minor/
H A Dlsq.hh101 bool recvTimingResp(PacketPtr pkt) override
102 { return lsq.recvTimingResp(pkt); }
108 void recvTimingSnoopReq(PacketPtr pkt) override
109 { return lsq.recvTimingSnoopReq(pkt); }
111 void recvFunctionalSnoop(PacketPtr pkt) override { }
720 bool recvTimingResp(PacketPtr pkt);
722 void recvTimingSnoopReq(PacketPtr pkt);
H A Dfetch1.hh77 bool recvTimingResp(PacketPtr pkt) argument
78 { return fetch.recvTimingResp(pkt); }
381 virtual bool recvTimingResp(PacketPtr pkt);
/gem5/src/mem/
H A Dpacket.cc312 Packet::copyResponderFlags(const PacketPtr pkt)
317 assert(!pkt->cacheResponding() || !cacheResponding());
318 flags.set(pkt->flags & RESPONDER_FLAGS);
407 Packet::matchBlockAddr(const PacketPtr pkt, const int blk_size) const argument
409 return matchBlockAddr(pkt->getBlockAddr(blk_size), pkt->isSecure(),
420 Packet::matchAddr(const PacketPtr pkt) const
422 return matchAddr(pkt->getAddr(), pkt->isSecure());
/gem5/src/mem/cache/tags/
H A Dbase.cc101 BaseTags::insertBlock(const PacketPtr pkt, CacheBlk *blk) argument
109 MasterID master_id = pkt->req->masterId();
114 blk->insert(extractTag(pkt->getAddr()), pkt->isSecure(), master_id,
115 pkt->req->taskId());
/gem5/src/dev/net/
H A Dns_gige.hh343 Tick writeConfig(PacketPtr pkt) override;
345 Tick read(PacketPtr pkt) override;
346 Tick write(PacketPtr pkt) override;
373 virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); } argument
H A Ddist_etherlink.hh192 bool recvPacket(EthPacketPtr pkt) { return txLink->transmit(pkt); } argument
H A Detherswitch.hh105 PortFifoEntry(EthPacketPtr pkt, Tick recv_tick, unsigned id) argument
106 : packet(pkt), recvTick(recv_tick), srcId(id) {}
/gem5/src/mem/ruby/system/
H A DSequencer.hh45 PacketPtr pkt; member in struct:SequencerRequest
51 : pkt(_pkt), m_type(_m_type), issue_time(_issue_time)
86 RequestStatus makeRequest(PacketPtr pkt);
152 void issueRequest(PacketPtr pkt, RubyRequestType type);
168 RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type);
/gem5/src/mem/ruby/network/simple/
H A DSwitch.cc175 Switch::functionalRead(Packet *pkt) argument
181 Switch::functionalWrite(Packet *pkt) argument
186 num_functional_writes += m_port_buffers[i]->functionalWrite(pkt);
/gem5/src/dev/arm/
H A Dgeneric_timer.cc568 GenericTimerMem::read(PacketPtr pkt) argument
570 const unsigned size(pkt->getSize());
571 const Addr addr(pkt->getAddr());
574 pkt->makeResponse();
586 pkt->setLE<uint64_t>(value);
588 pkt->setLE<uint32_t>(value);
597 GenericTimerMem::write(PacketPtr pkt) argument
599 const unsigned size(pkt->getSize());
603 const Addr addr(pkt->getAddr());
605 pkt
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H A Dgic_v2.hh461 Tick read(PacketPtr pkt) override;
466 Tick write(PacketPtr pkt) override;
477 * @param pkt packet to respond to
479 Tick readDistributor(PacketPtr pkt);
487 * @param pkt packet to respond to
489 Tick readCpu(PacketPtr pkt);
493 * @param pkt packet to respond to
495 Tick writeDistributor(PacketPtr pkt);
504 * @param pkt packet to respond to
506 Tick writeCpu(PacketPtr pkt);
[all...]
/gem5/src/mem/cache/prefetch/
H A Dbop.cc251 BOPPrefetcher::notifyFill(const PacketPtr& pkt) argument
253 // Only insert into the RR right way if it's the pkt is a HWP
254 if (!pkt->cmd.isHWPrefetch()) return;
256 Addr tag_y = tag(pkt->getAddr());
H A Dsbooe.cc97 SBOOEPrefetcher::notifyFill(const PacketPtr& pkt) argument
104 auto it = demandAddresses.find(pkt->getAddr());
/gem5/src/cpu/o3/
H A Ddyn_inst_impl.hh165 BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) argument
176 this->reqToVerify->setExtraData(pkt->req->getExtraData());
180 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
H A Dlsq_unit_impl.hh67 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
79 lsqPtr->writeback(inst, pkt);
83 delete pkt;
95 LSQUnit<Impl>::recvTimingResp(PacketPtr pkt) argument
97 auto senderState = dynamic_cast<LSQSenderState*>(pkt->senderState);
103 ret = req->recvTimingResp(pkt);
113 LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) argument
115 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
118 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
371 LSQUnit<Impl>::checkSnoop(PacketPtr pkt) argument
949 writeback(const DynInstPtr &inst, PacketPtr pkt) argument
[all...]
/gem5/src/mem/ruby/slicc_interface/
H A DAbstractController.hh144 void recvTimingResp(PacketPtr pkt);
145 Tick recvAtomic(PacketPtr pkt);
248 // Currently the pkt is handed to the coherence controller
250 bool recvTimingResp(PacketPtr pkt);
/gem5/src/dev/pci/
H A Dhost.hh282 Tick read(PacketPtr pkt) override;
283 Tick write(PacketPtr pkt) override;
/gem5/src/mem/ruby/network/garnet2.0/
H A DInputUnit.cc154 InputUnit::functionalWrite(Packet *pkt) argument
158 num_functional_writes += m_vcs[i]->functionalWrite(pkt);
H A DOutputUnit.cc165 OutputUnit::functionalWrite(Packet *pkt) argument
167 return m_out_buffer->functionalWrite(pkt);
/gem5/src/arch/arm/kvm/
H A Dgic.hh182 Tick read(PacketPtr pkt) override;
183 Tick write(PacketPtr pkt) override;
/gem5/src/cpu/testers/traffic_gen/
H A Ddram_gen.cc140 PacketPtr pkt = getPacket(addr, blocksize, local
150 return pkt;
/gem5/src/gpu-compute/
H A Dshader.hh169 bool processTimingPacket(PacketPtr pkt);
196 void functionalTLBAccess(PacketPtr pkt, int cu_id, BaseTLB::Mode mode);

Completed in 43 milliseconds

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