/gem5/src/dev/arm/ |
H A D | gic_v2m.hh | 108 virtual Tick read(PacketPtr pkt); 112 virtual Tick write(PacketPtr pkt);
|
H A D | energy_ctrl.hh | 124 * @param pkt Packet describing this request 127 Tick read(PacketPtr pkt) override; 130 * @param pkt Packet describing this request 133 Tick write(PacketPtr pkt) override;
|
H A D | rtc_pl031.hh | 116 * @param pkt The memory request. 119 Tick read(PacketPtr pkt) override; 123 * @param pkt The memory request. 126 Tick write(PacketPtr pkt) override;
|
H A D | timer_cpulocal.hh | 144 void read(PacketPtr pkt, Addr daddr); 147 void write(PacketPtr pkt, Addr daddr); 179 * @param pkt The memory request. 182 Tick read(PacketPtr pkt) override; 186 * @param pkt The memory request. 189 Tick write(PacketPtr pkt) override;
|
H A D | gic_v3_its.cc | 80 ItsProcess::run(PacketPtr pkt) argument 84 return (*coroutine)(pkt).get(); 98 a.pkt = new Packet(req, MemCmd::ReadReq); 99 a.pkt->dataStatic(ptr); 103 PacketPtr pkt = yield(a).get(); local 105 assert(pkt); 106 assert(pkt->getSize() >= size); 108 delete pkt; 122 a.pkt = new Packet(req, MemCmd::WriteReq); 123 a.pkt 127 PacketPtr pkt = yield(a).get(); local 237 PacketPtr pkt = yield.get(); local 819 read(PacketPtr pkt) argument 893 write(PacketPtr pkt) argument 1134 recvTimingResp(PacketPtr pkt) argument 1148 runProcess(ItsProcess *proc, PacketPtr pkt) argument 1160 runProcessTiming(ItsProcess *proc, PacketPtr pkt) argument 1191 runProcessAtomic(ItsProcess *proc, PacketPtr pkt) argument 1223 translate(PacketPtr pkt) argument [all...] |
/gem5/src/dev/virtio/ |
H A D | pci.hh | 56 Tick read(PacketPtr pkt); 57 Tick write(PacketPtr pkt);
|
/gem5/src/dev/x86/ |
H A D | speaker.hh | 72 Tick read(PacketPtr pkt) override; 74 Tick write(PacketPtr pkt) override;
|
H A D | i82094aa.hh | 100 Tick read(PacketPtr pkt) override; 101 Tick write(PacketPtr pkt) override; 109 bool recvResponse(PacketPtr pkt) override;
|
H A D | i8259.cc | 73 X86ISA::I8259::read(PacketPtr pkt) argument 75 assert(pkt->getSize() == 1); 76 switch(pkt->getAddr() - pioAddr) 81 pkt->setLE(IRR); 84 pkt->setLE(ISR); 89 pkt->setLE(IMR); 92 pkt->makeAtomicResponse(); 97 X86ISA::I8259::write(PacketPtr pkt) argument 99 assert(pkt->getSize() == 1); 100 uint8_t val = pkt [all...] |
/gem5/src/dev/mips/ |
H A D | malta_io.hh | 123 Tick read(PacketPtr pkt) override; 124 Tick write(PacketPtr pkt) override;
|
/gem5/src/mem/ruby/network/garnet2.0/ |
H A D | VirtualChannel.cc | 82 VirtualChannel::functionalWrite(Packet *pkt) argument 84 return m_input_buffer->functionalWrite(pkt);
|
H A D | flitBuffer.cc | 82 flitBuffer::functionalWrite(Packet *pkt) argument 87 if (m_buffer[i]->functionalWrite(pkt)) {
|
/gem5/src/cpu/testers/traffic_gen/ |
H A D | dram_rot_gen.cc | 128 PacketPtr pkt = getPacket(addr, blocksize, local 138 return pkt;
|
H A D | linear_gen.cc | 75 PacketPtr pkt = getPacket(nextAddr, blocksize, local 89 return pkt;
|
H A D | base_gen.cc | 71 PacketPtr pkt = new Packet(req, cmd); local 74 pkt->dataDynamic(pkt_data); 80 return pkt;
|
/gem5/src/dev/pci/ |
H A D | device.cc | 220 PciDevice::readConfig(PacketPtr pkt) argument 222 int offset = pkt->getAddr() & PCI_CONFIG_SIZE; 229 switch (pkt->getSize()) { 231 pkt->setLE<uint8_t>(0); 234 pkt->setLE<uint16_t>(0); 237 pkt->setLE<uint32_t>(0); 246 switch (pkt->getSize()) { 248 pkt->setLE<uint8_t>(config.data[offset]); 252 (uint32_t)pkt->getLE<uint8_t>()); 255 pkt 288 writeConfig(PacketPtr pkt) argument [all...] |
/gem5/src/mem/cache/ |
H A D | write_queue.cc | 61 WriteQueue::allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, argument 69 entry->allocate(blk_addr, blk_size, pkt, when_ready, order);
|
/gem5/src/arch/generic/ |
H A D | locked_mem.hh | 60 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument
|
/gem5/src/mem/ruby/system/ |
H A D | VIPERCoalescer.hh | 64 RequestStatus makeRequest(PacketPtr pkt);
|
H A D | DMASequencer.cc | 41 PacketPtr pkt) 44 pkt(pkt) 65 DMASequencer::makeRequest(PacketPtr pkt) argument 71 Addr paddr = pkt->getAddr(); 72 uint8_t* data = pkt->getPtr<uint8_t>(); 73 int len = pkt->getSize(); 74 bool write = pkt->isWrite(); 82 0, data, pkt)); 134 PacketPtr pkt 39 DMARequest(uint64_t start_paddr, int len, bool write, int bytes_completed, int bytes_issued, uint8_t *data, PacketPtr pkt) argument [all...] |
/gem5/src/cpu/testers/directedtest/ |
H A D | RubyDirectedTester.cc | 97 RubyDirectedTester::CpuPort::recvTimingResp(PacketPtr pkt) argument 99 tester->hitCallback(id, pkt->getAddr()); 104 delete pkt;
|
/gem5/src/cpu/testers/garnet_synthetic_traffic/ |
H A D | GarnetSyntheticTraffic.hh | 91 virtual bool recvTimingResp(PacketPtr pkt); 137 void completeRequest(PacketPtr pkt); 140 void sendPkt(PacketPtr pkt);
|
/gem5/src/cpu/o3/ |
H A D | lsq_impl.hh | 317 LSQ<Impl>::completeDataAccess(PacketPtr pkt) argument 319 auto senderState = dynamic_cast<LSQSenderState*>(pkt->senderState); 321 .completeDataAccess(pkt); 326 LSQ<Impl>::recvTimingResp(PacketPtr pkt) argument 328 if (pkt->isError()) 330 pkt->getAddr()); 332 auto senderState = dynamic_cast<LSQSenderState*>(pkt->senderState); 335 thread[cpu->contextToThread(senderState->contextId())].recvTimingResp(pkt); 337 if (pkt->isInvalidate()) { 350 pkt 364 recvTimingSnoopReq(PacketPtr pkt) argument 986 recvTimingResp(PacketPtr pkt) argument 999 recvTimingResp(PacketPtr pkt) argument [all...] |
/gem5/src/arch/arm/ |
H A D | locked_mem.hh | 65 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument 68 assert(pkt->isInvalidate() || pkt->isWrite()); 71 xc->getCpuPtr()->name(),pkt->getAddr(), 78 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
|
/gem5/src/dev/storage/ |
H A D | ide_ctrl.hh | 140 void dispatchAccess(PacketPtr pkt, bool read); 152 Tick writeConfig(PacketPtr pkt) override; 153 Tick readConfig(PacketPtr pkt) override; 157 Tick read(PacketPtr pkt) override; 158 Tick write(PacketPtr pkt) override;
|