Searched refs:objects (Results 126 - 150 of 312) sorted by relevance
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/gem5/src/cpu/ |
H A D | CPUTracers.py | 31 from m5.objects.InstTracer import InstTracer
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/gem5/src/cpu/kvm/ |
H A D | X86KvmCPU.py | 32 from m5.objects.BaseKvmCPU import BaseKvmCPU
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/gem5/src/cpu/o3/probe/ |
H A D | ElasticTrace.py | 40 from m5.objects.Probe import *
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/gem5/src/dev/i2c/ |
H A D | I2C.py | 40 from m5.objects.Device import BasicPioDevice
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/gem5/src/dev/mips/ |
H A D | Malta.py | 32 from m5.objects.BadDevice import BadDevice 33 from m5.objects.Device import BasicPioDevice 34 from m5.objects.Platform import Platform 35 from m5.objects.Uart import Uart8250
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/gem5/src/mem/probes/ |
H A D | MemTraceProbe.py | 40 from m5.objects.BaseMemProbe import BaseMemProbe
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/gem5/src/mem/qos/ |
H A D | QoSMemSinkCtrl.py | 39 from m5.objects.QoSMemCtrl import *
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/gem5/src/python/m5/ |
H A D | __init__.py | 51 from . import objects
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H A D | simulate.py | 57 from . import objects 68 "atomic" : objects.params.atomic, 69 "timing" : objects.params.timing, 70 "atomic_noncaching" : objects.params.atomic_noncaching, 80 root = objects.Root.getInstance() 119 # Create the C++ sim objects and connect ports 123 # Do a second pass to finish initializing the sim objects 137 # done once all of the CPP objects have been created and initialised so 163 root = objects.Root.getInstance() 191 # Try to drain all objects [all...] |
/gem5/src/gpu-compute/ |
H A D | LdsState.py | 38 from m5.objects.ClockedObject import ClockedObject
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/gem5/src/mem/ |
H A D | Bridge.py | 43 from m5.objects.ClockedObject import ClockedObject
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H A D | AbstractMemory.py | 43 from m5.objects.ClockedObject import ClockedObject
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H A D | MemDelay.py | 39 from m5.objects.ClockedObject import ClockedObject
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/gem5/src/mem/ruby/system/ |
H A D | GPUCoalescer.py | 38 from m5.objects.Sequencer import *
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H A D | RubySystem.py | 31 from m5.objects.ClockedObject import ClockedObject 32 from m5.objects.SimpleMemory import *
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/gem5/src/learning_gem5/part2/ |
H A D | SimpleCache.py | 32 from m5.objects.ClockedObject import ClockedObject
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/gem5/src/dev/serial/ |
H A D | Terminal.py | 45 from m5.objects.Serial import SerialDevice
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/gem5/configs/common/ |
H A D | MemConfig.py | 42 import m5.objects 58 return issubclass(cls, m5.objects.AbstractMemory) and \ 93 for name, cls in inspect.getmembers(m5.objects, is_mem_class): 118 if issubclass(cls, m5.objects.DRAMCtrl): 138 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(), 180 system.external_memory = m5.objects.ExternalSlave( 189 subsystem.external_memory = m5.objects.ExternalSlave( 206 if opt_elastic_trace_en and not issubclass(cls, m5.objects.SimpleMemory): 225 if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks: 229 if issubclass(cls, m5.objects [all...] |
/gem5/src/mem/cache/ |
H A D | Cache.py | 46 from m5.objects.ClockedObject import ClockedObject 47 from m5.objects.Compressors import BaseCacheCompressor 48 from m5.objects.Prefetcher import BasePrefetcher 49 from m5.objects.ReplacementPolicies import * 50 from m5.objects.Tags import *
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/gem5/src/systemc/core/ |
H A D | object.cc | 49 findObjectIn(Objects &objects, const std::string &name) argument 52 for (it = objects.begin(); it != objects.end(); it++) 60 addObject(Objects *objects, sc_core::sc_object *object) argument 62 objects->emplace(objects->end(), object); 66 popObject(Objects *objects, const std::string &name) argument 68 ObjectsIt it = findObjectIn(*objects, name); 69 assert(it != objects->end()); 70 std::swap(objects 75 nameIsUnique(Objects *objects, Events *events, const std::string &name) argument 298 findObject(const char *name, const Objects &objects) argument [all...] |
/gem5/src/mem/ruby/network/garnet2.0/ |
H A D | GarnetLink.py | 33 from m5.objects.ClockedObject import ClockedObject 34 from m5.objects.BasicLink import BasicIntLink, BasicExtLink
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/gem5/src/systemc/tlm_bridge/ |
H A D | TlmBridge.py | 28 from m5.objects.SystemC import SystemC_ScModule 32 from m5.objects.Tlm import TlmTargetSocket, TlmInitiatorSocket
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/gem5/src/dev/x86/ |
H A D | SouthBridge.py | 31 from m5.objects.Cmos import Cmos 32 from m5.objects.I8042 import I8042 33 from m5.objects.I82094AA import I82094AA 34 from m5.objects.I8237 import I8237 35 from m5.objects.I8254 import I8254 36 from m5.objects.I8259 import I8259 37 from m5.objects.Ide import IdeController 38 from m5.objects.PcSpeaker import PcSpeaker
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/gem5/configs/example/ |
H A D | sc_main.py | 33 from m5.objects import SystemC_Kernel, Root
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/gem5/src/cpu/testers/traffic_gen/ |
H A D | PyTrafficGen.py | 41 from m5.objects.BaseTrafficGen import *
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