Searched refs:mask (Results 126 - 141 of 141) sorted by relevance
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/gem5/src/base/loader/ |
H A D | elf_object.cc | 403 ElfObject::loadSomeSymbols(SymbolTable *symtab, int binding, Addr mask, argument 441 if (symtab->insert(value & mask, sym_name)) {
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/gem5/ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/ |
H A D | tlm_endian_conv.h | 768 sc_dt::uint64 mask = sizeof_databus-1; local 770 txn->set_address((a & ~mask) | 771 (sizeof_databus - (a & mask) - sizeof(DATAWORD)));
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/gem5/src/gpu-compute/ |
H A D | wavefront.cc | 784 const VectorMask& mask) 786 assert(mask.count()); 787 reconvergenceStack.emplace_back(new ReconvergenceStackEntry{pc, rpc, mask}); 783 pushToReconvergenceStack(uint32_t pc, uint32_t rpc, const VectorMask& mask) argument
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H A D | gpu_tlb.cc | 620 } else if ((IOPort & ~mask(2)) == 0xCFC) { 629 (IOPort & mask(2)));
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/gem5/src/arch/arm/ |
H A D | tlb.cc | 583 if (vaddr & mask(flags & AlignmentMask)) { 639 if (vaddr & mask(flags & AlignmentMask)) { 825 if (vaddr & mask(flags & AlignmentMask)) { 1078 if (vaddr & mask(flags & AlignmentMask)) { 1173 if ((!is_fetch) && (vaddr & mask(flags & AlignmentMask)) &&
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H A D | process.cc | 475 pc.set(getStartPC() & ~mask(1));
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H A D | table_walker.cc | 802 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || 830 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
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/gem5/src/arch/arm/kvm/ |
H A D | arm_cpu.cc | 57 #define EXTRACT_FIELD(val, mask, shift) \ 58 (((val) & (mask)) >> (shift)) 84 // There is no constant in the kernel headers defining the mask to use
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/gem5/src/dev/arm/ |
H A D | smmu_v3_transl.cc | 711 DPRINTF(SMMUv3, "%sWalkCache upd va=%#x mask=%#x asid=%#x vmid=%#x " 1300 int sizeMask = mask(smmu.regs.eventq_base & Q_BASE_SIZE_MASK); 1473 Addr mask = pte_size - 1; 1474 Addr base = addr & ~mask;
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/gem5/src/arch/x86/ |
H A D | decoder.cc | 724 MachInst maskVal = mask(size * 8) << (start * 8);
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H A D | process.cc | 919 // alignment mask. Also, it appears that there needs to be at least some 1104 uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32);
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/gem5/src/arch/riscv/ |
H A D | registers.hh | 656 const RegVal ISA_EXT_MASK = mask(26);
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/gem5/src/arch/arm/insts/ |
H A D | fplib.cc | 170 uint32_t mask = ((uint32_t)1 << 31) - 1; local 171 uint64_t a0 = a & mask; 172 uint64_t a1 = a >> 31 & mask; 173 uint64_t b0 = b & mask; 174 uint64_t b1 = b >> 31 & mask; 181 *x0 = (s0 & mask) | (s1 & mask) << 31 | s2 << 62;
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/gem5/src/python/m5/ |
H A D | params.py | 794 mask = 1 << bit1 797 mask |= 1 << bit2 798 self.masks[self.intlvBits - i - 1] = mask 869 code(' Addr mask;') 870 code(' _stream >> mask;') 871 code(' _masks.push_back(mask);')
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/gem5/src/arch/sparc/ |
H A D | tlb.cc | 1348 ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
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/gem5/ext/googletest/googletest/src/ |
H A D | gtest.cc | 1802 const UInt32 mask = (1 << 10) - 1; local 1804 (((first & mask) << 10) | (second & mask)) + 0x10000 :
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