Searched refs:mask (Results 101 - 125 of 141) sorted by relevance

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/gem5/src/mem/cache/tags/
H A Dfa_lru.hh94 /** A bit mask of the caches that fit this block. */
291 inAllCachesMask(mask(numTrackedCaches)),
368 /** A mask for all cache being tracked. */
/gem5/src/cpu/
H A Dbase.cc300 uint64_t mask = ~((uint64_t)(block_size - 1));
303 monitor.pAddr = pkt->getAddr() & mask;
325 uint64_t mask = ~((uint64_t)(block_size - 1));
340 monitor.pAddr = req->getPaddr() & mask;
/gem5/src/arch/mips/
H A Ddsp.hh198 void writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask);
199 uint32_t readDSPControl(uint32_t *dspctl, uint32_t mask);
/gem5/src/arch/x86/
H A Dremote_gdb.cc84 if ((va & ~mask(logBytes)) == (endVa & ~mask(logBytes)))
H A Ddecoder.hh124 partialImm &= mask(toGet * 8);
/gem5/src/systemc/tests/tlm/multi_sockets/
H A DMultiSocketSimpleSwitchAT.h113 ,sc_dt::uint64 mask = 0xffffffffffffffffULL){
119 m_masks.push_back(mask); //add the mask for this target
297 trans.set_address(trans.get_address()&m_masks[connInfo->fwID]); //mask address
/gem5/src/mem/cache/compressors/
H A Dbdi.cc270 const uint64_t mask = ULLONG_MAX>>((BYTES_PER_QWORD-sizeof(TB))*CHAR_BIT); local
289 value |= static_cast<uint64_t>((base + delta) & mask);
/gem5/src/dev/arm/
H A Dgic_v2.cc450 auto mask = data;
451 if (ix == 0) mask &= SGI_MASK; // Don't allow SGIs to be changed
452 getPendingInt(ctx, ix) |= mask;
459 auto mask = data;
460 if (ix == 0) mask &= SGI_MASK; // Don't allow SGIs to be changed
461 getPendingInt(ctx, ix) &= ~mask;
730 // mask some low-order priority bits per BPR value
H A Dhdlcd.cc590 HDLcd::setInterrupts(uint32_t ints, uint32_t mask) argument
594 int_mask = mask;
H A Dufs_device.hh454 uint32_t mask; member in struct:UFSHostDevice::transferStart
466 uint32_t mask; member in struct:UFSHostDevice::taskStart
/gem5/ext/systemc/src/sysc/datatypes/int/
H A Dsc_nbutils.cpp1681 const sc_digit mask = one_and_ones(nsr);
1695 (*viter++) = (((vval & mask) << BITS_PER_BYTE) | carry);
1755 sc_digit mask = one_and_ones(nsr);
1761 (*uiter++) = (((uval & mask) << nsl) | carry);
1824 sc_digit mask = one_and_ones(nsr);
1826 sc_digit carry = (fill & mask) << nsl;
1831 carry = (uval & mask) << nsl;
/gem5/src/systemc/dt/int/
H A Dsc_nbutils.cc1563 const sc_digit mask = one_and_ones(nsr);
1573 (*viter++) = (((vval & mask) << BITS_PER_BYTE) | carry);
1623 sc_digit mask = one_and_ones(nsr);
1629 (*uiter++) = (((uval & mask) << nsl) | carry);
1682 sc_digit mask = one_and_ones(nsr);
1684 sc_digit carry = (fill & mask) << nsl;
1689 carry = (uval & mask) << nsl;
/gem5/ext/systemc/src/sysc/datatypes/bit/
H A Dsc_lv_base.h332 sc_digit mask = SC_DIGIT_ONE << bi; local
333 m_data[wi] |= mask; // set bit to 1
334 m_ctrl[wi] |= mask; // set bit to 1
335 m_data[wi] &= value << bi | ~mask;
336 m_ctrl[wi] &= value >> 1 << bi | ~mask;
346 sc_digit mask = ~SC_DIGIT_ZERO >> (SC_DIGIT_SIZE - bi); local
347 if ( mask )
349 m_data[wi] &= mask;
350 m_ctrl[wi] &= mask;
/gem5/src/systemc/ext/dt/bit/
H A Dsc_lv_base.hh284 sc_digit mask = SC_DIGIT_ONE << bi; local
285 m_data[wi] |= mask; // set bit to 1
286 m_ctrl[wi] |= mask; // set bit to 1
287 m_data[wi] &= value << bi | ~mask;
288 m_ctrl[wi] &= value >> 1 << bi | ~mask;
296 sc_digit mask = ~SC_DIGIT_ZERO >> (SC_DIGIT_SIZE - bi); local
297 if (mask) {
298 m_data[wi] &= mask;
299 m_ctrl[wi] &= mask;
/gem5/src/cpu/kvm/
H A Dbase.cc253 // created since it manipulates the vCPU signal mask.
1158 BaseKvmCPU::setSignalMask(const sigset_t *mask) argument
1162 if (mask) {
1164 sizeof(struct kvm_signal_mask) + sizeof(*mask)));
1168 assert(sizeof(*mask) >= 8);
1170 memcpy(kvm_mask->sigset, mask, kvm_mask->len);
1174 panic("KVM: Failed to set vCPU signal mask (errno: %i)\n",
1242 panic("KVM: Failed get signal mask\n");
1244 // Request KVM to setup the same signal mask as we're currently
1255 panic("KVM: Failed mask th
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H A Dbase.hh538 * Set the signal mask used in kvmRun()
540 * This method allows the signal mask of the thread executing
542 * allows us to mask timer signals used to force KVM exits while
545 * The signal mask can be disabled by setting it to NULL.
547 * @param mask Signals to mask
549 void setSignalMask(const sigset_t *mask);
/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc107 return (base & mask(width)) >> shiftAmt;
114 base = sign_bit ? (base | ~mask(intWidth - shiftAmt)) : base;
115 return base & mask(intWidth);
170 tmp = sign_bit ? (tmp | ~mask(len + shiftAmt)) : tmp;
172 return tmp & mask(width);
/gem5/src/arch/x86/regs/
H A Dmisc.hh735 Bitfield<51, 12> physmask; // Range physical mask
798 Bitfield<31,0> mask; member in namespace:X86ISA
810 Bitfield<23> inv; // Invert mask
829 Bitfield<51,12> physmask; // Range physical mask
897 limit = (limit << 12) | mask(12);
905 panic_if(g && bits(limit, 11, 0) != mask(12),
/gem5/src/base/vnc/
H A Dvncserver.cc138 pixelFormat.redmax = pixelConverter.ch_r.mask;
139 pixelFormat.greenmax = pixelConverter.ch_g.mask;
140 pixelFormat.bluemax = pixelConverter.ch_b.mask;
/gem5/src/dev/net/
H A Di8254xGBe.cc215 regs.icr = regs.icr() & ~mask(30);
316 pkt->setLE<uint32_t>(regs.tdwba & mask(32));
572 regs.rdba.rdbal( val & ~mask(4));
580 regs.rdlen = val & ~mask(7);
610 regs.tdba.tdbal( val & ~mask(4));
618 regs.tdlen = val & ~mask(7);
650 regs.tdwba &= ~mask(32);
652 txDescCache.completionWriteback(regs.tdwba & ~mask(1),
653 regs.tdwba & mask(1));
656 regs.tdwba &= mask(3
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/gem5/src/systemc/ext/tlm_core/2/generic_payload/
H A Dendian_conv.hh920 sc_dt::uint64 mask = sizeof_databus - 1; local
922 txn->set_address((a & ~mask) |
923 (sizeof_databus - (a & mask) - sizeof(DATAWORD)));
/gem5/src/mem/
H A Dabstract_mem.cc213 Addr paddr = LockedAddr::mask(req->getPaddr());
244 Addr paddr = LockedAddr::mask(req->getPaddr());
/gem5/system/alpha/console/
H A Ddbmentry.S78 .mask 0x84000000, -8
/gem5/src/mem/ruby/system/
H A DDMASequencer.cc58 m_data_block_mask = mask(RubySystem::getBlockSizeBits());
/gem5/src/systemc/utils/
H A Dvcd.cc607 static_cast<uint64_t>(this->value()) & ::mask(sizeof(T) * 8);
609 if (::mask(w) < val) {

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