Searched refs:map (Results 26 - 50 of 198) sorted by relevance

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/gem5/site_scons/gem5_scons/
H A D__init__.py83 srcs = map(strip, source)
86 tgts = map(strip, target)
123 f = map(lambda s: s[com_pfx_len:], files)
/gem5/src/systemc/tests/tlm/multi_sockets/
H A DsimpleAddressMap.h24 #include <map>
29 * Simple address map implementation for the generic protocol.
34 typedef std::map<sc_dt::uint64, unsigned int> mapType;
35 typedef std::map<sc_dt::uint64, unsigned int>::iterator addressMapIterator;
62 * Print map
107 SC_REPORT_ERROR("SimpleAddressMap", "get_max() called on empty address map.");
119 SC_REPORT_ERROR("SimpleAddressMap", "get_min() called on empty address map.");
126 * Insert a slave into the address map
141 /// the address map
/gem5/src/systemc/utils/
H A Dreport.hh34 #include <map>
97 std::map<std::string, ReportMsgInfo> &reportMsgInfoMap();
98 std::map<int, std::string> &reportIdToMsgMap();
/gem5/src/sim/
H A Dcxx_config.hh56 #include <map>
110 std::map<std::string, ParamDesc *> parameters;
113 std::map<std::string, PortDesc *> ports;
232 extern std::map<std::string, CxxConfigDirectoryEntry *>
H A Dfd_array.hh155 std::map<std::string, int> _imap;
156 std::map<std::string, int> _oemap;
H A Ddvfs_handler.hh181 typedef std::map<DomainID, SrcClockDomain*> Domains;
256 typedef std::map<DomainID, UpdateEvent> UpdatePerfLevelEvents;
/gem5/src/arch/alpha/
H A Dremote_gdb.hh36 #include <map>
/gem5/util/minorview/
H A Dparse.py69 """map to a depth of 2. That is, given a list of lists, apply
71 return map(lambda l: map(f, l), ls)
H A Dcolours.py62 number_colour_code = map(name_to_colour, ['black', 'brown', 'red', 'orange',
/gem5/src/mem/ruby/structures/
H A DTimerTable.hh34 #include <map>
74 // use a std::map for the address map as this container is sorted
76 typedef std::map<Addr, Tick> AddressMap;
/gem5/ext/systemc/src/sysc/kernel/
H A Dsc_object_manager.h33 #include <map>
65 typedef std::map<std::string,table_entry> instance_table_t;
/gem5/src/arch/arm/linux/
H A Dsystem.hh47 #include <map>
77 /** This map stores a mapping of OS process IDs to internal Task IDs. The
81 std::map<uint32_t, uint32_t> taskMap;
/gem5/src/systemc/tlm_core/2/generic_payload/
H A Dphase.cc21 #include <map>
80 typedef std::map<std::type_index, key_type> type_map;
/gem5/src/arch/x86/bios/
H A DIntelMP.py137 map = {'INT' : 0, variable in class:X86IntelMPInterruptType
144 map = {'ConformPolarity' : 0, variable in class:X86IntelMPPolarity
150 map = {'ConformTrigger' : 0, variable in class:X86IntelMPTriggerMode
196 map = {"IOAddress" : 0, variable in class:X86IntelMPAddressType
223 map = {"ISACompatible" : 0, variable in class:X86IntelMPRangeList
/gem5/ext/pybind11/tests/
H A Dtest_stl_binders.cpp14 #include <map>
68 py::bind_map<std::map<std::string, double>>(m, "MapStringDouble");
72 py::bind_map<std::map<std::string, double const>>(m, "MapStringDoubleConst");
84 py::bind_map<std::map<int, E_nc>>(m, "MapENC");
85 m.def("get_mnc", &times_ten<std::map<int, E_nc>>, py::return_value_policy::reference);
/gem5/ext/dsent/
H A DDSENT.cc32 static void performTimingOpt(const map<String, String> &params, argument
95 static void reportTiming(const map<String, String> &params, Model *ms_model) argument
116 static Model *buildModel(const map<String, String> &params, argument
254 static TechModel* constructTechModel(const map<String, String>& params) argument
277 Model *initialize(const char *config_file_name, map<String, String> &config)
292 void finalize(map<String, String> &config, Model *ms_model)
304 void run(const map<String, String> &params, Model *ms_model, argument
305 map<string, double> &outputs)
328 const map<String, String> &config,
327 getEnvVar(const String& var_name_, const map<String, String> &config, Model *ms_model) const argument
H A Dinterface.cc44 // Create DSENT configuration map. This map is supposed to retain all
46 map<String, String> params;
143 map<string, double> outputs;
187 map<string, double> outputs;
/gem5/src/base/
H A Doutput.hh51 #include <map>
143 typedef std::map<std::string, OutputStream *> file_map_t;
146 typedef std::map<std::string, OutputDirectory *> dir_map_t;
/gem5/src/arch/riscv/
H A Disa.hh41 #include <map>
/gem5/src/cpu/o3/
H A Drename_map.cc66 assert(map.empty());
68 map.resize(size);
79 PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()];
94 map[arch_reg.flatIndex()] = renamed_reg;
/gem5/src/mem/
H A Dexternal_master.hh119 static std::map<std::string, Handler *> portHandlers;
H A Dexternal_slave.hh125 static std::map<std::string, Handler *> portHandlers;
/gem5/src/systemc/core/
H A Dmodule.hh35 #include <map>
57 std::map<std::string, int> counts;
/gem5/ext/dsent/libutil/
H A DCalculator.cc48 const map<String, String> &config,
50 map<string, double> &outputs)
177 const map<String, String> &config,
221 const map<String, String> &config,
246 const map<String, String> &config,
268 const map<String, String> &config,
47 evaluateString(const String& str_, const map<String, String> &config, DSENT::Model *ms_model, map<string, double> &outputs) argument
176 prim(istringstream& ist_, bool is_get_, const map<String, String> &config, DSENT::Model *ms_model) argument
220 term(istringstream& ist_, bool is_get_, const map<String, String> &config, DSENT::Model *ms_model) argument
245 expr(istringstream& ist_, bool is_get_, const map<String, String> &config, DSENT::Model *ms_model) argument
267 getEnvVar(const String& var_name_, const map<String, String> &config, DSENT::Model *ms_model) const argument
H A DMap.h26 #include <map>
33 using std::map;
38 typedef typename map<String, T>::iterator Iterator;
39 typedef typename map<String, T>::const_iterator ConstIterator;
40 typedef typename map<String, T>::size_type SizeType;
51 // Return the size of the map
53 // Check if the map is empty
72 // Merge a map. Values with same key will be overwritten.
74 // Returns a MapIterator referring to the first element in the map
77 // Returns a MapIterator referring to the past-the-end element in the map
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