Searched refs:enable (Results 26 - 50 of 75) sorted by relevance

123

/gem5/src/dev/arm/
H A Dtimer_a9global.hh78 Bitfield<0> enable; member in class:A9GlobalTimer::Timer
100 * interrupt enable */
H A Dkmi.hh71 Bitfield<2> enable; member in class:Pl050
H A Dtimer_a9global.cc177 old_enable = control.enable;
180 if ((old_enable == 0) && control.enable)
214 if (!control.enable)
235 if (!control.enable)
H A Dhdlcd.cc403 if (new_command.enable != command.enable) {
405 new_command.enable ? "on" : "off");
407 if (new_command.enable) {
H A Dhdlcd.hh208 Bitfield<0> enable; member in class:HDLcd
269 bool enabled() const { return command.enable; }
H A Dgeneric_timer.cc110 if (!_control.enable)
158 if ((new_ctl.enable && !new_ctl.imask) &&
159 !(_control.enable && !_control.imask)) {
168 _control.enable = new_ctl.enable;
/gem5/src/systemc/tests/systemc/kernel/process_control/test04/
H A Dtest04.cpp22 test04.cpp -- Test of interaction of suspend-resume, disable-enable, and
98 m_handle0.enable();
/gem5/src/systemc/tests/systemc/1666-2011-compliance/proc_ctrl_immed/
H A Dproc_ctrl_immed.cpp124 t.enable();
158 t.enable();
186 m.enable();
229 m.enable();
235 m.enable();
/gem5/src/arch/x86/bios/
H A DIntelMP.py102 enable = Param.Bool(True, 'if this processor is usable') variable in class:X86IntelMPProcessor
132 enable = Param.Bool(True, 'if this APIC is usable') variable in class:X86IntelMPIOAPIC
/gem5/src/systemc/core/
H A Dsc_process_handle.cc239 sc_process_handle::enable(sc_descendent_inclusion_info include_descendants) function in class:sc_core::sc_process_handle
242 SC_REPORT_WARNING(SC_ID_EMPTY_PROCESS_HANDLE_, "enable()");
245 _gem5_process->enable(include_descendants == SC_INCLUDE_DESCENDANTS);
H A Dprocess.cc132 Process::enable(bool inc_kids) function in class:sc_gem5::Process
136 forEachKid([](Process *p) { p->enable(true); });
/gem5/src/base/
H A Dtrace.cc91 enable() function in namespace:Trace
H A Dstatistics.cc279 Info::enable() function in class:Stats::Info
284 VectorInfo::enable() function in class:Stats::VectorInfo
294 VectorDistInfo::enable() function in class:Stats::VectorDistInfo
304 Vector2dInfo::enable() function in class:Stats::Vector2dInfo
552 enable() function in namespace:Stats
H A Dtrace.hh123 void enable();
157 // selectively enable tracing statements. To use DPRINTF, there must
/gem5/src/systemc/tests/systemc/1666-2011-compliance/disable_enable/
H A Ddisable_enable.cpp75 t.enable();
/gem5/src/systemc/tests/systemc/1666-2011-compliance/proc_ctrl_elab/
H A Dproc_ctrl_elab.cpp118 td5.enable();
207 td3.enable();
297 td2.enable();
307 td4.enable();
/gem5/src/systemc/tests/systemc/1666-2011-compliance/proc_ctrl_timeout/
H A Dproc_ctrl_timeout.cpp115 t3.enable();
116 t4.enable();
167 t5.enable();
/gem5/src/arch/arm/
H A Dpmu.hh141 // Cycle counter divider enable
143 // Export enable
147 // Long Cycle counter enable
327 virtual void enable() = 0;
382 void enable() override;
389 void enable() override {}
H A Dpmu.cc431 const bool enable(global_enable && (reg_pmcnten & (1 << i)));
432 if (ctr.enabled != enable) {
433 ctr.enabled = enable;
449 enable();
480 PMU::RegularEvent::enable() function in class:ArmISA::PMU::RegularEvent
586 warn("Can't enable PMU counter of type '0x%x': "
/gem5/src/systemc/ext/core/
H A Dsc_process_handle.hh107 // These should be protected, but I think this is to enable catch by
197 void enable(sc_descendent_inclusion_info include_descendants=
/gem5/ext/systemc/src/sysc/kernel/
H A Dsc_process_handle.h94 inline void enable(
293 // enable this object instance's target.
295 inline void sc_process_handle::enable(sc_descendant_inclusion_info descendants) function in class:sc_core::sc_process_handle
300 SC_REPORT_WARNING( SC_ID_EMPTY_PROCESS_HANDLE_, "enable()");
/gem5/src/systemc/tests/systemc/1666-2011-compliance/async_reset/
H A Dasync_reset.cpp196 enable();
230 enable();
247 ct2.enable();
248 t2.enable();
544 void enable() function in struct:Top
546 ct.enable();
547 t.enable();
548 m.enable();
/gem5/src/systemc/tests/systemc/1666-2011-compliance/proc_ctrl/
H A Dproc_ctrl.cpp123 t1.reset(); // Reset takes priority over enable
129 t1.reset(); // Reset takes priority over enable
135 t1.enable();
156 t1.enable();
/gem5/src/python/m5/
H A Dmain.py404 debug.flags[flag].enable()
408 e = event.create(trace.enable, event.Event.Debug_Enable_Pri)
411 trace.enable()
/gem5/util/tlm/src/
H A Dsim_control.cc98 Trace::enable();

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