Searched refs:desc (Results 76 - 100 of 155) sorted by relevance

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/gem5/src/sim/power/
H A Dthermal_domain.cc83 .desc("Temperature in centigrate degrees")
/gem5/src/dev/virtio/
H A Dblock.hh170 void onNotifyDescriptor(VirtDescriptor *desc);
H A Dconsole.hh139 void onNotifyDescriptor(VirtDescriptor *desc);
H A Dfs9p.cc143 VirtIO9PBase::FSQueue::onNotifyDescriptor(VirtDescriptor *desc) argument
145 DPRINTF(VIO9P, "Got input data descriptor (len: %i)\n", desc->size());
149 desc->chainRead(0, (uint8_t *)&header, sizeof(header));
153 desc->chainRead(sizeof(header), data, sizeof(data));
156 parent.pendingTransactions[header.tag] = desc;
/gem5/src/arch/x86/
H A Dsystem.hh63 SegDescriptor desc, bool longmode);
/gem5/src/gpu-compute/
H A Dfetch_stage.cc104 .desc("For each instruction fetch request recieved record how many "
H A Dlocal_memory_pipeline.cc124 .desc("total number of cycles LDS data are delayed before updating "
H A Dtlb_coalescer.cc532 .desc("Number of uncoalesced TLB accesses")
537 .desc("Number of coalesced TLB accesses")
542 .desc("Number of cycles spent in queue")
547 .desc("Number of cycles spent in queue for all incoming reqs")
552 .desc("Avg. latency over all incoming pkts")
/gem5/src/dev/net/
H A DEthernet.py51 def __init__(self, desc):
52 super(EtherInt, self).__init__(ETHERNET_ROLE, desc)
55 def __init__(self, desc):
56 super(VectorEtherInt, self).__init__(ETHERNET_ROLE, desc)
168 wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
169 fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
170 fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
171 wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
/gem5/src/mem/ruby/system/
H A DGPUCoalescer.cc1306 .desc("loads that hit in the TCP")
1310 .desc("TCP to TCP load transfers")
1314 .desc("loads that hit in the TCC")
1318 .desc("loads that miss in the GPU")
1323 .desc("stores that hit in the TCP")
1327 .desc("TCP to TCP store transfers")
1331 .desc("stores that hit in the TCC")
1335 .desc("stores that miss in the GPU")
1341 .desc("loads that hit in the TCP")
1345 .desc("TC
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/gem5/src/python/pybind11/
H A Ddebug.cc101 .def("desc", &Debug::Flag::desc)
/gem5/src/base/stats/
H A Dtext.hh102 Output *initText(const std::string &filename, bool desc);
/gem5/src/python/m5/stats/
H A D__init__.py84 wrapped_f(urlparse.urlsplit("text://stats.txt?desc=False")) ->
85 f("stats.txt", desc=False)
137 def _textFactory(fn, desc=True):
142 disabled by setting the desc parameter to False.
145 * desc (bool): Output stat descriptions (default: True)
148 text://stats.txt?desc=False
152 return _m5.stats.initText(fn, desc)
155 def _hdf5Factory(fn, chunking=10, desc=True, formulas=True):
180 * desc (bool): Output stat descriptions (default: True)
184 h5://stats.h5?desc
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/gem5/src/cpu/o3/
H A Ddecode_impl.hh129 .desc("Number of cycles decode is idle")
133 .desc("Number of cycles decode is blocked")
137 .desc("Number of cycles decode is running")
141 .desc("Number of cycles decode is unblocking")
145 .desc("Number of cycles decode is squashing")
149 .desc("Number of times decode resolved a branch")
153 .desc("Number of times decode detected a branch misprediction")
157 .desc("Number of times decode detected an instruction incorrectly"
162 .desc("Number of instructions handled by decode")
166 .desc("Numbe
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H A Dcommit_impl.hh155 .desc("The number of squashed insts skipped by commit")
160 .desc("The number of times commit has been forced to stall to "
166 .desc("The number of times a branch was mispredicted")
172 .desc("Number of insts commited each cycle")
179 .desc("Number of instructions committed")
186 .desc("Number of ops (including micro ops) committed")
193 .desc("Number of s/w prefetches committed")
200 .desc("Number of memory references committed")
207 .desc("Number of loads committed")
214 .desc("Numbe
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/gem5/src/mem/ruby/network/
H A DMessageBuffer.cc410 .desc("Number of times this buffer did not have N slots available")
415 .desc("Average number of messages in buffer")
420 .desc("Number of times messages were stalled")
425 .desc("Average occupancy of buffer capacity")
430 .desc("Average number of cycles messages are stalled in this MB")
/gem5/util/stats/
H A Dinfo.py380 p.desc = self.desc
400 d.desc = self.desc
424 def display(self, name, desc, flags, precision):
494 def display(self, name, desc, flags, precision):
528 SimpleDist.display(self, name, desc, flags, precision)
588 self.dist.display(self.name, self.desc, self.flags, self.precision)
628 desc = sd
630 desc
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/gem5/src/cpu/o3/probe/
H A Delastic_trace.cc893 .desc("Number of register dependencies recorded during tracing")
898 .desc("Number of commit order (rob) dependencies for a store recorded"
904 .desc("Number of loads that got assigned issue order dependency"
910 .desc("Number of stores that got assigned issue order dependency"
916 .desc("Number of non load/store insts that got assigned issue order"
922 .desc("No. of nodes filtered out before writing the output trace")
927 .desc("Maximum number or dependents on any instruction")
932 .desc("Maximum size of the temporary store during the run")
937 .desc("Maximum size of register dependency map")
/gem5/src/dev/arm/
H A Dflash_device.cc485 .desc("Number of Garbage collector activations")
492 .desc("Histogram of write addresses")
497 .desc("Histogram of read addresses")
502 .desc("Histogram of file system accesses")
509 .desc("Histogram of write latency")
514 .desc("Histogram of read latency")
H A Dsmmu_v3_caches.cc93 .desc("Average number lookups per second")
98 .desc("Total number of lookups")
106 .desc("Average number misses per second")
111 .desc("Total number of misses")
119 .desc("Average number updates per second")
124 .desc("Total number of updates")
132 .desc("Average hit rate")
139 .desc("Number of insertions (not replacements)")
1238 .desc("Average number lookups per second")
1243 .desc("Tota
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/gem5/src/cpu/minor/
H A Dfetch2.cc616 .desc("Number of integer instructions successfully decoded")
621 .desc("Number of floating point instructions successfully decoded")
626 .desc("Number of SIMD instructions successfully decoded")
631 .desc("Number of memory load instructions successfully decoded")
636 .desc("Number of memory store instructions successfully decoded")
641 .desc("Number of memory atomic instructions successfully decoded")
/gem5/src/sim/
H A Dvoltage_domain.cc138 .desc("Voltage in Volts")
/gem5/src/learning_gem5/part2/
H A Dsimple_cache.cc433 .desc("Number of hits")
437 .desc("Number of misses")
441 .desc("Ticks for misses to the cache")
446 .desc("The ratio of hits to the total accesses to the cache")
/gem5/src/cpu/pred/
H A Dtage_base.cc723 .desc("Number of times TAGE Longest Match is the provider and "
728 .desc("Number of times TAGE Alt Match is the provider and "
733 .desc("Number of times TAGE Alt Match is the bimodal and it is the "
738 .desc("Number of times there are no hits on the TAGE tables "
743 .desc("Number of times TAGE Longest Match is the provider and "
748 .desc("Number of times TAGE Alt Match is the provider and "
753 .desc("Number of times TAGE Alt Match is the bimodal and it is the "
758 .desc("Number of times there are no hits on the TAGE tables "
763 .desc("Number of times TAGE Longest Match is the provider, "
768 .desc("Numbe
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/gem5/src/arch/arm/
H A Dtlb.cc447 .desc("ITB inst hits")
452 .desc("ITB inst misses")
457 .desc("ITB inst accesses")
462 .desc("DTB read hits")
467 .desc("DTB read misses")
472 .desc("DTB read accesses")
477 .desc("DTB write hits")
482 .desc("DTB write misses")
487 .desc("DTB write accesses")
492 .desc("DT
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