Searched refs:dcache (Results 26 - 29 of 29) sorted by relevance

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/gem5/src/cpu/
H A DBaseCPU.py247 self.dcache = dc
250 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
/gem5/ext/mcpat/
H A Dcore.cc798 : McPATComponent(_xml_data), dcache(NULL), LSQ(NULL), LoadQ(NULL),
810 // Check if there is a dcache child:
812 dcache = NULL;
823 strcmp(name, "dcache") == 0) {
824 dcache = new CacheUnit(childXML, &interface_ip);
825 children.push_back(dcache);
3082 if (dcache) {
3083 output_data += dcache->output_data;
3534 if (dcache) {
3535 delete dcache;
[all...]
/gem5/src/mem/ruby/system/
H A DSequencer.cc62 m_dataCache_ptr = p->dcache;
H A DGPUCoalescer.cc137 m_dataCache_ptr = p->dcache;

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