/gem5/src/dev/arm/ |
H A D | rv_ctrl.cc | 60 Addr daddr = pkt->getAddr() - pioAddr; local 62 switch(daddr) { 122 daddr); 136 Addr daddr = pkt->getAddr() - pioAddr; local 137 switch (daddr) { 198 daddr, pkt->getLE<uint32_t>());
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H A D | hdlcd.cc | 243 const Addr daddr(pkt->getAddr() - pioAddr); 246 daddr, pkt->getSize()); 248 const uint32_t data(readReg(daddr)); 249 DPRINTF(HDLcd, "read register 0x%04x: 0x%x\n", daddr, data); 263 const Addr daddr(pkt->getAddr() - pioAddr); 266 daddr, pkt->getSize()); 268 DPRINTF(HDLcd, "write register 0x%04x: 0x%x\n", daddr, data); 270 writeReg(daddr, data);
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/gem5/src/dev/serial/ |
H A D | uart8250.cc | 102 Addr daddr = pkt->getAddr() - pioAddr; local 104 DPRINTF(Uart, " read register %#x\n", daddr); 106 switch (daddr) { 171 DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32); 184 Addr daddr = pkt->getAddr() - pioAddr; local 186 DPRINTF(Uart, " write register %#x value %#x\n", daddr, 189 switch (daddr) {
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/gem5/src/dev/net/ |
H A D | sinic.hh | 168 uint8_t ®Data8(Addr daddr) { return *((uint8_t *)®s + daddr); } argument 169 uint32_t ®Data32(Addr daddr) { return *(uint32_t *)®Data8(daddr); } argument 170 uint64_t ®Data64(Addr daddr) { return *(uint64_t *)®Data8(daddr); } argument 270 // Fault iprRead(Addr daddr, ContextID cpu, uint64_t &result);
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H A D | sinicreg.hh | 184 regInfo(Addr daddr) argument 222 return info[daddr / 4]; 226 regValid(Addr daddr) argument 228 if (daddr > Regs::Size) 231 if (regInfo(daddr).size == 0)
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H A D | ns_gige.cc | 194 Addr daddr = pkt->getAddr() & 0xfff; local 196 daddr, pkt->getAddr(), pkt->getSize()); 201 if (daddr > LAST && daddr <= RESERVED) { 203 } else if (daddr > RESERVED && daddr <= 0x3FC) { 205 } else if (daddr >= MIB_START && daddr <= MIB_END) { 212 } else if (daddr > 0x3FC) 219 switch (daddr) { 415 Addr daddr = pkt->getAddr() & 0xfff; local [all...] |
H A D | sinic.cc | 224 Addr daddr = pkt->getAddr() - BARAddrs[0]; local 225 Addr index = daddr >> Regs::VirtualShift; 226 Addr raddr = daddr & Regs::VirtualMask; 230 cpu, index, daddr, pkt->getAddr(), pkt->getSize()); 236 info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize()); 240 info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize()); 259 info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize(), value); 273 Device::iprRead(Addr daddr, ContextID cpu, uint64_t &result) 275 if (!regValid(daddr)) 276 panic("invalid address: da=%#x", daddr); 309 Addr daddr = pkt->getAddr() - BARAddrs[0]; local [all...] |
H A D | i8254xGBe.cc | 173 Addr daddr; local 175 if (!getBAR(pkt->getAddr(), bar, daddr)) 184 DPRINTF(Ethernet, "Read device register %#X\n", daddr); 191 switch (daddr) { 344 if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) && 345 !IN_RANGE(daddr, REG_RAL, RCV_ADDRESS_TABLE_SIZE*8) && 346 !IN_RANGE(daddr, REG_MTA, MULTICAST_TABLE_SIZE*4) && 347 !IN_RANGE(daddr, REG_CRCERRS, STATS_REGS_SIZE)) 348 panic("Read request to unknown register number: %#x\n", daddr); 361 Addr daddr; local [all...] |
/gem5/src/dev/alpha/ |
H A D | tsunami_pchip.cc | 82 Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6;; 88 switch(daddr) { 150 panic("Default in PChip Read reached reading 0x%x\n", daddr); 166 Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6; 172 switch(daddr) { 231 panic("Default in PChip write reached reading 0x%x\n", daddr);
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H A D | tsunami_cchip.cc | 85 Addr daddr = (pkt->getAddr() - pioAddr); local 92 if (daddr & TSDEV_CC_BDIMS) 94 pkt->setLE(dim[(daddr >> 4) & 0x3F]); 98 if (daddr & TSDEV_CC_BDIRS) 100 pkt->setLE(dir[(daddr >> 4) & 0x3F]); 197 Addr daddr = pkt->getAddr() - pioAddr; local 209 if (daddr & TSDEV_CC_BDIMS) 211 int number = (daddr >> 4) & 0x3F;
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/gem5/src/dev/pci/ |
H A D | copy_engine.hh | 106 void channelRead(PacketPtr pkt, Addr daddr, int size); 107 void channelWrite(PacketPtr pkt, Addr daddr, int size);
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