Searched refs:assert (Results 76 - 100 of 647) sorted by relevance

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/gem5/src/cpu/testers/directedtest/
H A DInvalidateGenerator.cc105 assert(m_address == address);
108 assert(m_active_read_node == proc);
120 assert(m_active_inv_node == proc);
/gem5/src/gpu-compute/
H A Dsimple_pool_manager.cc69 assert(numRegions * minAllocatedElements(size) <= poolSize());
77 assert(_reservedGroups > 0);
92 assert(_nxtFreeIdx < poolSize());
/gem5/src/mem/
H A Ddramsim2.cc106 assert(!retryResp);
107 assert(!responseQueue.empty());
129 assert(!sendResponseEvent.scheduled());
224 assert(wrapper.canAccept());
245 assert(retryResp);
264 assert(pkt->isResponse());
289 assert(cycle == divCeil(curTick() - startTick,
296 assert(p != outstandingReads.end());
308 assert(nbrOutstandingReads != 0);
317 assert(cycl
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H A Dpacket.hh541 assert(isRequest());
589 assert(isRequest());
590 assert(!flags.isSet(CACHE_RESPONDING));
649 assert(cacheResponding());
650 assert(!responderHadWritable());
671 assert(cmd.isWrite() &&
685 assert(cmd.isClean());
686 assert(!flags.isSet(SATISFIED));
722 assert(isResponse());
726 void copyError(Packet *pkt) { assert(pk
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H A Dpacket_queue.cc69 assert(waitingOnRetry);
114 assert(when >= curTick());
117 assert(!pkt->isExpressSnoop());
132 // assert(waitingOnRetry || sendEvent.scheduled());
160 assert(!sendEvent.scheduled());
194 assert(!waitingOnRetry);
195 assert(deferredPacketReady());
223 assert(!waitingOnRetry);
/gem5/src/dev/arm/
H A Da9scu.cc56 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
57 assert(pkt->getSize() == 4);
93 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
/gem5/src/mem/ruby/structures/
H A DCacheMemory.cc82 assert(m_cache_num_sets > 1);
84 assert(m_cache_num_set_bits > 0);
105 assert(address == makeLineAddress(address));
115 assert(tag == makeLineAddress(tag));
131 assert(tag == makeLineAddress(tag));
148 assert(set < m_cache_num_sets); function
151 assert (way < m_cache_assoc);
166 assert(address == makeLineAddress(address));
193 assert(address == makeLineAddress(address));
216 assert(addres
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/gem5/ext/libelf/
H A Dgelf_dyn.c27 #include <assert.h>
52 assert(ec == ELFCLASS32 || ec == ELFCLASS64);
66 assert(msz > 0);
108 assert(ec == ELFCLASS32 || ec == ELFCLASS64);
121 assert(msz > 0);
H A Dgelf_rel.c29 #include <assert.h>
53 assert(ec == ELFCLASS32 || ec == ELFCLASS64);
67 assert(msz > 0);
109 assert(ec == ELFCLASS32 || ec == ELFCLASS64);
122 assert(msz > 0);
H A Dgelf_rela.c29 #include <assert.h>
53 assert(ec == ELFCLASS32 || ec == ELFCLASS64);
67 assert(msz > 0);
110 assert(ec == ELFCLASS32 || ec == ELFCLASS64);
123 assert(msz > 0);
H A Dgelf_symshndx.c29 #include <assert.h>
55 assert(ec == ELFCLASS32 || ec == ELFCLASS64);
70 assert(msz > 0);
102 assert(ec == ELFCLASS32 || ec == ELFCLASS64);
116 assert(msz > 0);
H A Dlibelf_allocate.c33 #include <assert.h>
71 assert(e != NULL);
72 assert(e->e_kind == ELF_K_NONE);
111 assert(STAILQ_EMPTY(&e->e_u.e_elf.e_scn));
184 assert(s != NULL);
192 assert((d->d_flags & LIBELF_F_MALLOCED) == 0);
199 assert(e != NULL);
/gem5/src/cpu/
H A Dtranslation.hh87 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
103 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
116 assert(outstanding);
255 assert(state);
256 assert(mode == state->mode);
/gem5/src/mem/ruby/common/
H A DNetDest.cc41 assert(bitIndex(newElement.num) < m_bits[vecIndex(newElement)].getSize());
48 assert(m_bits.size() == netDest.getSize());
58 assert(MachineType_base_level((MachineType)(machine + 1)) -
72 assert(m_bits.size() == netDest.getSize());
140 assert(count() > 0);
194 assert(m_bits.size() == orNetDest.getSize());
206 assert(m_bits.size() == andNetDest.getSize());
218 assert(m_bits.size() == other_netDest.getSize());
230 assert(m_bits.size() == test.getSize());
250 assert(m_bit
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/gem5/ext/systemc/src/tlm_utils/
H A Dsimple_target_socket.h91 assert(!sc_core::sc_get_curr_simcontext()->elaboration_done());
99 assert(!sc_core::sc_get_curr_simcontext()->elaboration_done());
106 assert(!sc_core::sc_get_curr_simcontext()->elaboration_done());
114 assert(!sc_core::sc_get_curr_simcontext()->elaboration_done());
163 assert(0); exit(1);
216 assert(!m_mod || m_mod == mod);
229 assert(!m_mod || m_mod == mod);
242 assert(!m_mod || m_mod == mod);
255 assert(!m_mod || m_mod == mod);
267 assert(m_mo
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/gem5/src/systemc/tests/include/
H A DSimpleATInitiator1.h243 assert(0); exit(1);
249 assert(0); exit(1);
259 assert(t == sc_core::SC_ZERO_TIME); // FIXME: can t != 0?
266 assert(t == sc_core::SC_ZERO_TIME); // FIXME: can t != 0?
274 assert(dynamic_cast<mytransaction_type*>(&trans));
276 assert(myTrans);
290 assert(0); exit(1);
297 assert(!mEndResponseQueue.empty());
302 assert(trans);
307 assert(
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H A DSimpleBusAT.h107 assert(portId < NR_OF_TARGETS);
113 assert(it != mPendingTransactions.end());
139 assert(0); exit(1);
162 assert(0); exit(1);
176 assert(it != mPendingTransactions.end());
198 assert(0); exit(1);
208 assert(r == tlm::TLM_COMPLETED);
239 assert(false); exit(1);
253 assert(false); exit(1);
267 assert(portI
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/gem5/tests/test-progs/asmtest/src/riscv/env/v/
H A Dvm.c57 #define assert(x) do { \ macro
96 assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
103 assert(user_l3pt[addr/PGSIZE] & PTE_A);
106 assert(user_l3pt[addr/PGSIZE] & PTE_D);
125 assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
132 assert(!(user_l3pt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT);
140 assert(node);
149 assert(user_mapping[addr/PGSIZE].addr == 0);
175 assert(tf->epc % 4 == 0);
183 assert(!"illega
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/gem5/src/dev/sparc/
H A Dmm_disk.cc64 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
75 assert(bytes_written == SectorSize);
81 assert(bytes_read == SectorSize);
122 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
133 assert(bytes_written == SectorSize);
139 assert(bytes_read == SectorSize);
183 assert(bytes_read == SectorSize);
/gem5/src/cpu/kvm/
H A Dperfevent.cc97 assert(attached());
164 assert(!attached());
197 assert(attached());
198 assert(ringBuffer == NULL);
220 assert(attached());
227 assert(attached());
237 assert(attached());
/gem5/src/mem/ruby/network/garnet2.0/
H A DRoutingUnit.cc171 assert(outport != -1);
187 assert(num_rows > 0 && num_cols > 0);
204 assert(!(x_hops == 0 && y_hops == 0));
208 assert(inport_dirn == "Local" || inport_dirn == "West");
211 assert(inport_dirn == "Local" || inport_dirn == "East");
217 assert(inport_dirn != "North");
221 assert(inport_dirn != "South");
/gem5/src/mem/ruby/network/
H A DMessageBuffer.cc131 assert(msg_ptr);
163 assert(delta > 0);
184 assert(arrival_time > current_time);
201 assert(msg_ptr != NULL);
203 assert(current_time >= msg_ptr->getLastEnqueueTime() &&
220 assert(m_consumer != NULL);
229 assert(isReady(current_time));
293 assert(isReady(current_time));
310 assert(m->getLastEnqueueTime() <= schdTick);
329 assert(m_stall_msg_ma
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/gem5/src/cpu/simple/
H A Dexec_context.hh182 assert(reg.isIntReg());
192 assert(reg.isIntReg());
203 assert(reg.isFloatReg());
214 assert(reg.isFloatReg());
224 assert(reg.isVecReg());
234 assert(reg.isVecReg());
245 assert(reg.isVecReg());
258 assert(reg.isVecReg());
293 assert(reg.isVecReg());
324 assert(re
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/gem5/src/mem/cache/
H A Dmshr.cc126 assert(!mshr->downstreamPending);
158 assert(!pkt->hasData());
261 assert(target);
278 assert(target->matchBlockAddr(targets.front().pkt, blkSize));
285 assert(downstreamPending);
295 assert(!inService);
316 assert(targets.empty());
318 assert(deferredTargets.isReset());
331 assert(pkt->cmd != MemCmd::HardPFReq);
507 assert((i
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/gem5/src/cpu/o3/
H A Dstore_set.cc121 assert(load_index < SSITSize && store_index < SSITSize);
138 assert(new_set < LFSTSize);
150 assert(load_SSID < LFSTSize);
169 assert(load_SSID < LFSTSize && store_SSID < LFSTSize);
216 assert(index < SSITSize);
224 assert(store_SSID < LFSTSize);
245 assert(index < SSITSize);
256 assert(inst_SSID < LFSTSize);
285 assert(index < SSITSize);
300 assert(store_SSI
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