Searched refs:assert (Results 176 - 200 of 647) sorted by relevance

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/gem5/src/gpu-compute/
H A Dfetch_unit.cc89 assert (curWave);
169 assert(computeUnit->sqcTLBPort->retries.size() > 0);
210 assert(pkt->req->hasPaddr());
211 assert(pkt->req->hasSize());
270 assert(wavefront->instructionBuffer.empty());
276 assert(wavefront->instructionBuffer.size() <= 4);
282 assert(inst_ptr);
H A Ddispatcher.cc129 assert(pkt->getAddr() >= pioAddr);
130 assert(pkt->getAddr() < pioAddr + pioSize);
138 assert(!offset);
139 assert(pkt->getSize() == 8);
145 assert(offset + pkt->getSize() < sizeof(HsaQueueEntry));
159 assert(pkt->getAddr() >= pioAddr);
160 assert(pkt->getAddr() < pioAddr + pioSize);
243 assert(offset < sizeof(HsaQueueEntry));
314 assert(ndRangeMap[kern_id].dispatchId == kern_id);
/gem5/src/cpu/o3/
H A Dregfile.cc142 assert(intRegIds[reg_idx].index() == reg_idx);
149 assert(floatRegIds[reg_idx].index() == reg_idx);
156 assert(vecRegIds[reg_idx].index() == reg_idx);
158 assert(vecElemIds[reg_idx * NumVecElemPerVecReg +
160 assert(vecElemIds[reg_idx * NumVecElemPerVecReg +
175 assert(vecPredRegIds[reg_idx].index() == reg_idx);
182 assert(ccRegIds[reg_idx].index() == reg_idx);
/gem5/src/cpu/testers/rubytest/
H A DRubyTester.cc117 assert(writePorts.size() > 0 && readPorts.size() > 0);
126 assert(m_num_readers == m_num_cpus);
159 assert(if_name == "cpuDataPort");
209 assert(idx >= 0 && idx < readPorts.size());
217 assert(idx >= 0 && idx < writePorts.size());
239 assert(check_ptr != NULL);
249 assert(check_ptr != NULL);
/gem5/src/mem/
H A Dbridge.cc177 assert(outstandingResponses != respQueueLimit);
226 assert(transmitList.size() != reqQueueLimit);
249 assert(!transmitList.empty());
253 assert(req.tick <= curTick());
287 assert(!transmitList.empty());
291 assert(resp.tick <= curTick());
303 assert(outstandingResponses != 0);
/gem5/src/arch/sparc/
H A Dtlb.cc141 assert(entry < size && entry >= 0);
173 assert(PTE.valid());
185 assert(i != lookupTable.end());
349 assert(entry < size);
359 assert(entry < size);
426 assert(req->getArchFlags() == ASI_IMPLICIT);
849 assert(translation);
874 assert(va == 0);
894 assert(va == 0);
898 assert(v
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/gem5/src/dev/
H A Dintel_8254_timer.hh226 assert(num < 3);
233 assert(num < 3);
240 assert(num < 3);
/gem5/src/mem/ruby/network/garnet2.0/
H A DInputUnit.cc97 assert(m_vcs[vc]->get_state() == IDLE_);
110 assert(m_vcs[vc]->get_state() == ACTIVE_);
129 assert(pipe_stages > 1);
H A DVirtualChannel.cc74 assert(m_vc_state.first == ACTIVE_ && m_vc_state.second <= time);
/gem5/src/mem/probes/
H A Dmem_footprint.cc96 assert(set->size() <= limit);
112 assert(cacheLines.size() <= cacheLinesAll.size());
113 assert(pages.size() <= pagesAll.size());
/gem5/src/arch/hsail/insts/
H A Dmem.hh116 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
122 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
128 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
134 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
140 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
145 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
152 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
347 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
353 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
359 assert((operandInde
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/gem5/src/arch/arm/insts/
H A Dmacromem.cc337 assert(uop == &microOps[numMicroops]);
464 assert(regs > 0 && regs <= 4);
465 assert(regs % elems == 0);
517 assert(regs == 4);
522 assert(regs == 3);
527 assert(regs == 4 || regs == 2);
543 assert(uopIdx == numMicroops);
547 assert(uopPtr);
561 assert(regs > 0 && regs <= 4);
562 assert(reg
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/gem5/src/arch/x86/
H A Dcpuid.cc98 assert(vendorStringSize >= 12);
120 assert(nameStringSize >= offset + 16);
156 assert(vendorStringSize >= 12);
/gem5/src/learning_gem5/part2/
H A Dsimple_memobj.cc115 assert(blockedPacket != nullptr);
149 assert(blockedPacket != nullptr);
187 assert(blocked);
/gem5/src/arch/x86/regs/
H A Dmisc.hh415 assert(index >= 0 && index < NumCRegs);
422 assert(index >= 0 && index < NumDRegs);
429 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END -
437 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END -
445 assert(index >= 0 && index < (MISCREG_MC_CTL_END -
453 assert(index >= 0 && index < (MISCREG_MC_STATUS_END -
461 assert(index >= 0 && index < (MISCREG_MC_ADDR_END -
469 assert(index >= 0 && index < (MISCREG_MC_MISC_END -
477 assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END -
485 assert(inde
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/gem5/src/cpu/
H A Dsimple_thread.hh288 assert(flatIndex < TheISA::NumIntRegs);
299 assert(flatIndex < TheISA::NumFloatRegs);
310 assert(flatIndex < TheISA::NumVecRegs);
321 assert(flatIndex < TheISA::NumVecRegs);
336 assert(flatIndex < TheISA::NumVecRegs);
377 assert(flatIndex < TheISA::NumVecRegs);
411 assert(flatIndex < TheISA::NumVecRegs);
422 assert(flatIndex < TheISA::NumVecPredRegs);
433 assert(flatIndex < TheISA::NumVecPredRegs);
446 assert(
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/gem5/ext/fputils/tests/
H A Dfp80_cvtf.c34 #include <assert.h>
/gem5/src/arch/x86/insts/
H A Dmacroop.hh65 assert(numMicroops);
/gem5/src/base/
H A Dchunk_generator.hh85 assert(chunkSize == 0 || isPowerOf2(chunkSize));
/gem5/src/sim/
H A Dvoltage_domain.hh106 assert(src_clock_dom->voltageDomain() == this);
/gem5/src/mem/ruby/common/
H A DHistogram.cc74 assert(m_binsize != -1);
90 assert(value >= 0);
117 assert(index < m_data.size());
160 assert(m_binsize == hist.getBinSize());
/gem5/ext/systemc/src/sysc/kernel/
H A Dsc_cor.h92 : m_simc( simc ) { assert( simc != 0 ); }
H A Dsc_module_name.h87 assert( m_module_p == module_p );
/gem5/src/dev/alpha/
H A Dtsunami.cc63 assert(alphaSystem);
/gem5/src/dev/net/
H A Dpktfifo.hh109 assert(avail() >= len);
124 assert(ptr->length);
125 assert(_reserved <= ptr->length);
165 assert(prev != fifo.end());

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