/gem5/src/systemc/ext/tlm_core/2/generic_payload/ |
H A D | endian_conv.hh | 100 bus data sizes and address alignment except for the the following 118 because the data reordering function is much simpler and no address 128 - the address must be aligned to the bus width 174 sc_dt::uint64 address; // Used by generic, word. member in class:tlm::tlm_endian_context 221 // 1) only the address attribute of a transaction 389 tc->address, tc->new_address, txn->get_data_length(), 425 tc->address = txn->get_address(); 447 tc->address, new_address, new_length, tc->data_ptr, 0, 451 s_width, sizeof_databus, tc->address, new_address, 459 new_stream_width, s_width, sizeof_databus, tc->address, [all...] |
H A D | gp.hh | 185 void set_address(const sc_dt::uint64 address) { m_address = address; } argument 261 /* - m_address : Transaction base address (byte-addressing). */ 280 /* the address increment between each beat is greater */
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/gem5/src/dev/arm/ |
H A D | gic_v3_its.cc | 149 const Addr address = base + (device_id * sizeof(dte)); local 151 DPRINTF(ITS, "Writing DTE at address %#x: %#x\n", address, dte); 153 doWrite(yield, address, &dte, sizeof(dte)); 160 const Addr address = itt_base + (event_id * sizeof(itte)); local 162 doWrite(yield, address, &itte, sizeof(itte)); 164 DPRINTF(ITS, "Writing ITTE at address %#x: %#x\n", address, itte); 172 const Addr address = base + (collection_id * sizeof(cte)); local 174 doWrite(yield, address, 184 const Addr address = base + (device_id * sizeof(dte)); local 197 const Addr address = itt_base + (event_id * sizeof(itte)); local 210 const Addr address = base + (collection_id * sizeof(cte)); local [all...] |
H A D | ufs_device.cc | 912 * Determine address ranges 1233 Addr address = 0x00; local 1269 address = UFSHCIMem.TMUTMRLBAU; 1271 address = (count * size) + (address << 32) + 1279 task_info.address = address; 1285 writeDevice(&taskEventQueue.back(), false, address, size, 1298 address = UFSHCIMem.TRUTRLBAU; 1300 address 1706 transferDone(Addr responseStartAddr, uint32_t req_pos, struct UTPUPIURSP request_out, uint32_t size, Addr address, uint8_t* destination, bool finished, uint32_t lun_id) argument [all...] |
H A D | smmu_v3_defs.hh | 367 Bitfield<63, 12> address; member in struct:SMMUCommand 373 uint64_t address = (uint64_t)(dw1.address) << 12; local 374 return address;
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H A D | gic_v3.hh | 159 getRedistributorByAddr(Addr address) const;
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H A D | ufs_device.hh | 297 * baseAddr: Lower 32bit physical address DW-0 298 * upperAddr: Upper 32bit physical address DW-1 311 * commandUPIU: Command UPIU Frame address 312 * responseUPIU: Response UPIU Frame address 335 * commandDescBaseAddrLo: UCD base address low DW-4 336 * commandDescBaseAddrHi: UCD base address high DW-5 443 Addr address; member in struct:UFSHostDevice::transferDoneInfo 455 Addr address; member in struct:UFSHostDevice::transferStart 467 Addr address; member in struct:UFSHostDevice::taskStart 891 * the host has no indication whatsoever which LU to address [all...] |
H A D | flash_device.cc | 165 FlashDevice::accessDevice(uint64_t address, uint32_t amount, Callback *event, argument 172 uint64_t logic_page_addr = address / pageSize; 187 " logic address 0x%8x\n", index, 234 stats.fileSystemAccess.sample(address); 379 //use block as the logical start address of the block 488 /** Histogram of address accesses*/
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/gem5/src/arch/x86/bios/ |
H A D | IntelMP.py | 65 local_apic = Param.UInt32(0xFEE00000, 'address of the local APIC') 134 address = Param.UInt32(0xfec00000, 'address of this APIC') variable in class:X86IntelMPIOAPIC 206 bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to') 208 'address type used to access bus') 209 address = Param.Addr(0, 'starting address of the mapping') variable in class:X86IntelMPAddrSpaceMapping
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/gem5/src/dev/pci/ |
H A D | copy_engine.hh | 116 void fetchDescriptor(Addr address); 120 void fetchNextAddr(Addr address);
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H A D | host.hh | 124 * Calculate the physical address of an IO location on the PCI 127 * @param addr Address in the PCI IO address space 128 * @return Address in the system's physical address space. 133 * Calculate the physical address of a non-prefetchable memory 134 * location in the PCI address space. 136 * @param addr Address in the PCI memory address space 137 * @return Address in the system's physical address space. 142 * Calculate the physical address of a prefetchable memory 143 * location in the PCI address space. 145 * @param addr Address in the PCI DMA memory address spac [all...] |
/gem5/include/gem5/ |
H A D | m5ops.h | 43 void m5_arm(uint64_t address);
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/gem5/src/mem/ruby/system/ |
H A D | RubySystem.cc | 401 Addr address(pkt->getAddr()); 402 Addr line_address = makeLineAddress(address); 407 DPRINTF(RubySystem, "Functional Read request for %#x\n", address); 416 // address in read only, read write and busy states. 459 "addr: %#x on cacheline: %#x.", address, line_address); 468 // a read write copy of the given address. Any valid copy would suffice 485 // and writes the data portion of those that hold the address specified
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/gem5/src/arch/hsail/ |
H A D | operand.hh | 633 // if the address expression is 32b, then the hi 639 * a signed type to avoid address calculation errors 664 fatal("can't do calcUniform() on register-based address\n"); 674 Addr address = calcUniformBase(); local 679 addrVec[lane] = address + reg.template get<uint32_t>(w, lane); 681 addrVec[lane] = address + reg.template get<Addr>(w, lane); 691 Addr address = calcUniformBase(); local 693 return address + reg.template get<Addr>(w, lane); 731 uint64_t address = calcUniformBase(); local 734 addrVec[lane] = address; [all...] |
H A D | operand.cc | 330 "address calculations where the operand is not a variable\n"); 383 uint64_t address = offset; local 387 address += storageElement->offset; 390 return address;
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/gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/ |
H A D | cycle_model.h | 54 o_add, // 11bit destination address 55 o_ladd // 16bit destination address 125 int address; member in struct:stack_el
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/gem5/ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/ |
H A D | tlm_endian_conv.h | 100 bus data sizes and address alignment except for the the following 118 because the data reordering function is much simpler and no address 128 - the address must be aligned to the bus width 176 sc_dt::uint64 address; // used by generic, word member in class:tlm::tlm_endian_context 214 // 1) only the address attribute of a transaction 346 txn->get_streaming_width(), tc->stream_width, sizeof_databus, tc->address, 377 tc->address = txn->get_address(); 398 new_stream_width, s_width, sizeof_databus, tc->address, 403 new_stream_width, s_width, sizeof_databus, tc->address, 410 new_stream_width, s_width, sizeof_databus, tc->address, [all...] |
/gem5/system/alpha/console/ |
H A D | dbmentry.S | 38 /* return address and padding to octaword align */ 76 stq ra, 0(sp) # Place return address on the stack 117 ldq ra, 0(sp) # restore return address
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/gem5/util/m5/ |
H A D | lua_gem5Op.c | 44 uint64_t address = lua_tointeger(L, 1); local 45 m5_arm(address);
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/gem5/src/systemc/tests/include/ |
H A D | SimpleLTInitiator2_DMI.h | 159 // - if the address is not covered by a DMI region try to acquire DMI 171 sc_dt::uint64 address = trans.get_address(); //save original address local 175 trans.set_address(address); 232 // Test for transport_dbg, this one should fail in bus_dmi as we address 234 // FIXME: use a configurable address
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H A D | SimpleLTInitiator3_DMI.h | 157 // - if the address is not covered by a DMI region try to acquire DMI 169 sc_dt::uint64 address = trans.get_address(); //save original address local 173 trans.set_address(address);
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/gem5/src/mem/cache/prefetch/ |
H A D | base.cc | 60 : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0), 76 : address(addr), pc(pfi.pc), masterId(pfi.masterId), validPC(pfi.validPC), 211 panic("Request must have a physical address");
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/gem5/ext/libfdt/ |
H A D | fdt_ro.c | 70 int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) argument 73 *address = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->address);
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H A D | fdt_rw.c | 151 int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size) argument 163 re->address = cpu_to_fdt64(address);
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/gem5/ext/systemc/src/sysc/qt/md/ |
H A D | ksr1.s | 30 # KSR convention: on procedure calls, load both the procedure address 31 # and a pointer to a constant block. The address of function `f' is 32 # `f$TXT', and the constant block address is `f'. The constant block 43 # address. 66 # procedure address. Callers that don't want (or aren't expecting) a 156 # argument (%i2). Note that the address of the helper's constant 158 # address. 255 # because we don't use it, and we load the return address specially
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