Searched refs:VecRegContainer (Results 26 - 29 of 29) sorted by relevance

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/gem5/src/cpu/o3/
H A Dcpu.cc1216 -> const VecRegContainer&
1225 -> VecRegContainer&
1283 FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
1339 -> const VecRegContainer&
1349 -> VecRegContainer&
1421 FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val,
/gem5/src/arch/riscv/
H A Dregisters.hh76 using VecRegContainer = ::DummyVecRegContainer;
/gem5/src/arch/arm/
H A Disa.hh693 static void zeroSveVecRegUpperPart(VecRegContainer &vc,
H A Disa.cc2166 ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)

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