Searched refs:ULL (Results 26 - 50 of 93) sorted by relevance

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/gem5/src/systemc/channel/
H A Dsc_signal.cc41 sc_core::sc_prim_channel(name), _changeStamp(~0ULL),
110 sig(_sig), firstPort(nullptr), proc(nullptr), writeStamp(~0ULL)
138 sig(_sig), proc(nullptr), writeStamp(~0ULL)
162 ScSignalBase(_name), _posStamp(~0ULL), _negStamp(~0ULL)
/gem5/src/arch/riscv/
H A Disa.cc65 miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x14112D;
69 miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) |
70 (1ULL << FS_OFFSET);
95 return (miscRegFile[counteren] & (1ULL << (hpmcounter))) > 0;
/gem5/src/cpu/kvm/
H A Dtimer.cc109 ts.it_value.tv_sec = hostNs(ticks) / 1000000000ULL;
110 ts.it_value.tv_nsec = hostNs(ticks) % 1000000000ULL;
141 const uint64_t res_ns(ts.tv_sec * 1000000000ULL + ts.tv_nsec);
/gem5/src/arch/generic/
H A Dmmapped_ipr.hh60 const Addr IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF);
/gem5/src/base/
H A Dcondcodes.hh57 return ((src1 ^ ~src2) & (src1 ^ dest)) & (1ULL << shift);
H A Dtypes.hh50 #define ULL(N) ((uint64_t)N##ULL) macro
65 const Tick MaxTick = ULL(0xffffffffffffffff);
/gem5/src/arch/sparc/
H A Dinterrupts.hh108 interrupts[int_num] |= ULL(1) << index;
109 intStatus |= ULL(1) << int_num;
119 interrupts[int_num] &= ~(ULL(1) << index);
121 intStatus &= ~(ULL(1) << int_num);
H A Dtlb.hh47 const Addr StartVAddrHole = ULL(0x0000800000000000);
48 const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
49 const Addr VAddrAMask = ULL(0xFFFFFFFF);
50 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
H A Dua2005.cc161 setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF));
272 return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF);
275 return ULL(0x3e) << 48 |
276 ULL(0x23) << 32 |
277 ULL(0x20) << 24 |
342 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
343 setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
369 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
/gem5/src/cpu/pred/
H A Dbi_mode.cc61 choiceThreshold = (ULL(1) << (choiceCtrBits - 1)) - 1;
62 takenThreshold = (ULL(1) << (globalCtrBits - 1)) - 1;
63 notTakenThreshold = (ULL(1) << (globalCtrBits - 1)) - 1;
144 globalHistoryReg[tid] &= (historyRegisterMask & ~ULL(1));
H A Dtournament.cc118 localThreshold = (ULL(1) << (localCtrBits - 1)) - 1;
119 globalThreshold = (ULL(1) << (globalCtrBits - 1)) - 1;
120 choiceThreshold = (ULL(1) << (choiceCtrBits - 1)) - 1;
169 globalHistory[tid] &= (historyRegisterMask & ~ULL(1));
172 localHistoryTable[local_history_idx] & (localPredictorMask & ~ULL(1));
H A Dtage_sc_l.cc195 return (index & ((ULL(1) << (logTagTableSizes[bank])) - 1));
203 a = a & ((ULL(1) << size) - 1);
204 a1 = (a & ((ULL(1) << logTagTableSizes[bank]) - 1));
208 a2 = ((a2 << bank) & ((ULL(1) << logTagTableSizes[bank]) - 1))
215 a = ((a << bank) & ((ULL(1) << logTagTableSizes[bank]) - 1))
226 ((ULL(1) << (logTagTableSizes[0])) - 1));
254 tHist.pathHist = (tHist.pathHist & ((ULL(1) << pathHistBits) - 1));
324 if (tCounter >= ((ULL(1) << logUResetPeriod))) {
H A Dtage_base.cc132 const uint64_t bimodalTableSize = ULL(1) << logTagTableSizes[0];
204 return ((pc_in >> instShiftAmt) & ((ULL(1) << (logTagTableSizes[0])) - 1));
212 A = A & ((ULL(1) << size) - 1);
213 A1 = (A & ((ULL(1) << logTagTableSizes[bank]) - 1));
215 A2 = ((A2 << bank) & ((ULL(1) << logTagTableSizes[bank]) - 1))
218 A = ((A << bank) & ((ULL(1) << logTagTableSizes[bank]) - 1))
237 return (index & ((ULL(1) << (logTagTableSizes[bank])) - 1));
249 return (tag & ((ULL(1) << tagTableTagWidths[bank]) - 1));
455 ((ULL(1) << (nHistoryTables - bi->hitBank - 1)) - 1);
491 if ((tCounter & ((ULL(
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/gem5/src/arch/arm/insts/
H A Dvfp.cc227 const uint64_t qnan = single ? 0x7fc00000 : ULL(0x7ff8000000000000);
236 uint64_t bitMask = ULL(0x1) << (sizeof(fpType) * 8 - 1);
257 const uint64_t qnan = single ? 0x7fc00000 : ULL(0x7ff8000000000000);
275 uint64_t bitMask = ULL(0x1) << (sizeof(fpType) * 8 - 1);
299 (!single && (val == bitsToFp(ULL(0x0010000000000000), junk) ||
300 val == bitsToFp(ULL(0x8010000000000000), junk)))
375 if (mid == bitsToFp(ULL(0x0010000000000000), junk) ||
376 mid == bitsToFp(ULL(0x8010000000000000), junk)) {
786 (ULL(0x3fd) << 52) | (bits(opBits, 31) << 63),
790 (ULL(
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H A Dfplib.cc79 #define FP16_EXP_INF ((1ULL << FP16_EXP_BITS) - 1)
80 #define FP32_EXP_INF ((1ULL << FP32_EXP_BITS) - 1)
81 #define FP64_EXP_INF ((1ULL << FP64_EXP_BITS) - 1)
87 #define FP16_EXP(x) ((x) >> FP16_MANT_BITS & ((1ULL << FP16_EXP_BITS) - 1))
88 #define FP32_EXP(x) ((x) >> FP32_MANT_BITS & ((1ULL << FP32_EXP_BITS) - 1))
89 #define FP64_EXP(x) ((x) >> FP64_MANT_BITS & ((1ULL << FP64_EXP_BITS) - 1))
91 #define FP16_MANT(x) ((x) & ((1ULL << FP16_MANT_BITS) - 1))
92 #define FP32_MANT(x) ((x) & ((1ULL << FP32_MANT_BITS) - 1))
93 #define FP64_MANT(x) ((x) & ((1ULL << FP64_MANT_BITS) - 1))
374 return fp16_pack(0, FP16_EXP_INF, 1ULL << (FP16_MANT_BIT
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/gem5/src/dev/alpha/
H A Dtsunami_cchip.cc223 bitvector = ULL(1) << x;
316 bitvector = ULL(1) << x;
387 uint64_t cpumask = ULL(1) << cpunum;
412 uint64_t cpumask = ULL(1) << i;
433 uint64_t cpumask = ULL(1) << cpunum;
458 uint64_t cpumask = ULL(1) << i;
471 uint64_t bitvector = ULL(1) << interrupt;
489 uint64_t bitvector = ULL(1) << interrupt;
/gem5/src/arch/power/
H A Dpagetable.hh50 static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
/gem5/src/dev/net/
H A Detherdump.cc98 pkthdr.microseconds = (curTick() / SimClock::Int::us) % ULL(1000000);
/gem5/src/dev/arm/
H A Damba_device.cc51 const uint64_t AmbaVendor = ULL(0xb105f00d00000000);
H A Dpl011.hh119 static const uint64_t AMBA_ID = ULL(0xb105f00d00341011);
/gem5/src/dev/serial/
H A Dterminal.cc292 #define MORE_PENDING (ULL(1) << 61)
293 #define RECEIVE_SUCCESS (ULL(0) << 62)
294 #define RECEIVE_NONE (ULL(2) << 62)
295 #define RECEIVE_ERROR (ULL(3) << 62)
/gem5/src/dev/x86/
H A Dcmos.hh78 rtc(this, name() + ".rtc", p->time, true, ULL(5000000000),
/gem5/src/arch/alpha/
H A Dvtophys.cc99 paddr = vaddr & ~ULL(1);
H A Dpagetable.hh43 static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
/gem5/src/arch/arm/freebsd/
H A Dsystem.cc133 bootReleaseAddr = ra & ~ULL(0x7F);

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