Searched refs:SimObject (Results 126 - 150 of 357) sorted by relevance
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| /gem5/src/sim/ |
| H A D | cxx_manager.hh | 113 /** SimObject indexed by name */
114 std::map<std::string, SimObject *> objectsByName;
120 std::list<SimObject *> objectsInOrder;
131 void bindPort(SimObject *masterObject, const std::string &masterPort,
132 PortID masterPortIndex, SimObject *slaveObject,
138 void bindMasterPort(SimObject *object,
154 /** Class for resolving SimObject names to SimObjects usable by the
166 SimObject *resolveSimObject(const std::string &name)
167 { return &(configManager.getObject<SimObject>(name)); }
189 /** Bind the ports of a single SimObject */
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| H A D | sub_system.cc | 47 : SimObject(p)
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| H A D | System.py | 43 from m5.SimObject import *
54 class System(SimObject):
69 thermal_components = VectorParam.SimObject([],
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| H A D | Process.py | 29 from m5.SimObject import *
34 class Process(SimObject):
71 class EmulatedDriver(SimObject):
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| /gem5/src/arch/x86/bios/ |
| H A D | acpi.hh | 67 class RSDP : public SimObject
84 class SysDescTable : public SimObject
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| /gem5/src/dev/arm/ |
| H A D | gic_v2m.hh | 62 class Gicv2mFrame : public SimObject
71 SimObject(p), addr(p->addr), spi_base(p->spi_base), spi_len(p->spi_len)
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| /gem5/src/arch/mips/ |
| H A D | interrupts.hh | 49 class Interrupts : public SimObject
60 Interrupts(Params * p) : SimObject(p)
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| /gem5/src/mem/qos/ |
| H A D | policy_fixed_prio.cc | 69 FixedPriorityPolicy::initMasterObj(const SimObject* master, uint8_t priority)
72 this->pair<const SimObject*, uint8_t>(master, priority));
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| H A D | policy_fixed_prio.hh | 76 * the master's SimObject pointer and priority value.
78 * @param master master's SimObject pointer to lookup.
81 void initMasterObj(const SimObject* master, uint8_t priority);
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| /gem5/src/arch/power/ |
| H A D | isa.hh | 50 class ISA : public SimObject
138 using SimObject::startup;
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| /gem5/src/arch/riscv/ |
| H A D | isa.hh | 65 class ISA : public SimObject
94 using SimObject::startup;
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| /gem5/src/cpu/pred/ |
| H A D | indirect.hh | 40 class IndirectPredictor : public SimObject
47 : SimObject(params)
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| /gem5/src/dev/x86/ |
| H A D | south_bridge.hh | 46 class SouthBridge : public SimObject
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| H A D | south_bridge.cc | 39 SouthBridge::SouthBridge(const Params *p) : SimObject(p),
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| /gem5/src/mem/ruby/structures/ |
| H A D | AbstractReplacementPolicy.hh | 39 class AbstractReplacementPolicy : public SimObject
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| /gem5/src/mem/probes/ |
| H A D | base.cc | 45 : SimObject(p)
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| /gem5/src/dev/serial/ |
| H A D | serial.hh | 92 class SerialDevice : public SimObject
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| H A D | serial.cc | 47 : SimObject(p), interfaceCallback(nullptr)
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| /gem5/src/systemc/core/ |
| H A D | kernel.hh | 42 * the simulation. It receives gem5 SimObject lifecycle callbacks (init,
47 class Kernel : public SimObject
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| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | PyTrafficGen.py | 39 from m5.SimObject import *
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| /gem5/src/sim/power/ |
| H A D | power_model.hh | 49 class SimObject;
56 class PowerModelState : public SimObject
115 * A PowerModel is a class containing a power model for a SimObject.
118 class PowerModel : public SimObject
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| /gem5/src/arch/arm/ |
| H A D | ArmTLB.py | 40 from m5.SimObject import SimObject
81 class ArmStage2MMU(SimObject):
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| /gem5/src/gpu-compute/ |
| H A D | X86GPUTLB.py | 39 from m5.SimObject import SimObject
42 class X86PagetableWalker(SimObject):
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| /gem5/src/mem/ |
| H A D | CommMonitor.py | 42 from m5.SimObject import SimObject
46 class CommMonitor(SimObject):
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| H A D | XBar.py | 45 from m5.SimObject import SimObject
122 class SnoopFilter(SimObject):
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