| /gem5/src/dev/pci/ |
| H A D | PciDevice.py | 54 pci_bus = Param.Int("PCI bus")
55 pci_dev = Param.Int("PCI device number")
56 pci_func = Param.Int("PCI function code")
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| /gem5/src/arch/arm/ |
| H A D | ArmPMU.py | 174 cycleEventId = Param.Int(ARCH_EVENT_CORE_CYCLES, "Cycle event id")
176 eventCounters = Param.Int(31, "Number of supported PMU counters")
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| H A D | ArmTLB.py | 68 size = Param.Int(64, "TLB size")
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| H A D | semihosting.cc | 517 return retOK(curTick() / (SimClock::Int::s / 100));
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| /gem5/src/mem/cache/tags/ |
| H A D | base.cc | 159 if (age / SimClock::Int::us < 10) { // <10us
161 } else if (age / SimClock::Int::us < 100) { // <100us
163 } else if (age / SimClock::Int::ms < 1) { // <1ms
165 } else if (age / SimClock::Int::ms < 10) { // <10ms
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| /gem5/src/dev/net/ |
| H A D | Ethernet.py | 109 bufsz = Param.Int(10000, "tap buffer size")
130 maxlen = Param.Int(96, "max portion of packet data to dump")
146 rx_desc_cache_size = Param.Int(64,
148 tx_desc_cache_size = Param.Int(64,
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| H A D | i8254xGBe.hh | 166 Tick intClock() { return SimClock::Int::ns * 1024; }
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| H A D | i8254xGBe.cc | 705 Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval();
813 Tick t = curTick() + SimClock::Int::ns * 256 * regs.itr.interval();
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| /gem5/src/dev/arm/ |
| H A D | rtc_pl031.cc | 72 data = timeVal + ((curTick() - lastWrittenTick) / SimClock::Int::s);
172 Tick ticks_until = SimClock::Int::s * seconds_until;
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| H A D | energy_ctrl.cc | 104 result = dvfsHandler->transLatency() / SimClock::Int::ns;
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| /gem5/src/dev/ |
| H A D | mc146818.hh | 76 parent(_parent), offset(SimClock::Int::s)
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| H A D | mc146818.cc | 184 schedule(tickEvent, curTick() + SimClock::Int::s / 2);
342 parent->schedule(this, curTick() + SimClock::Int::s);
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| /gem5/src/mem/cache/ |
| H A D | Cache.py | 72 block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
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| /gem5/src/mem/ |
| H A D | dramsim2.cc | 151 schedule(tickEvent, curTick() + wrapper.clockPeriod() * SimClock::Int::ns);
290 wrapper.clockPeriod() * SimClock::Int::ns));
318 wrapper.clockPeriod() * SimClock::Int::ns));
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| H A D | drampower.cc | 98 timingSpec.clkPeriod = (p->tCK / (double)(SimClock::Int::ns));
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| H A D | xbar.cc | 114 panic_if(pkt->headerDelay > SimClock::Int::us,
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| /gem5/src/sim/power/ |
| H A D | thermal_model.cc | 241 schedule(stepEvent, curTick() + SimClock::Int::s * _step);
278 schedule(stepEvent, curTick() + SimClock::Int::s * _step);
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| /gem5/src/dev/serial/ |
| H A D | uart8250.cc | 79 static const Tick interval = 225 * SimClock::Int::ns;
208 if (curTick() - lastTxInt > 225 * SimClock::Int::ns) {
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| /gem5/ext/googletest/googletest/test/ |
| H A D | gtest-typed-test_test.cc | 310 INSTANTIATE_TYPED_TEST_CASE_P(Int, TypedTestP1, int);
311 INSTANTIATE_TYPED_TEST_CASE_P(Int, TypedTestP2, Types<int>);
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| /gem5/ext/googletest/googletest/include/gtest/internal/ |
| H A D | gtest-port.h | 2476 typedef int Int; typedef in class:testing::internal::TypeWithSize
2485 typedef __int64 Int; typedef in class:testing::internal::TypeWithSize
2488 typedef long long Int; // NOLINT
2494 typedef TypeWithSize<4>::Int Int32;
2496 typedef TypeWithSize<8>::Int Int64;
2498 typedef TypeWithSize<8>::Int TimeInMillis; // Represents time in milliseconds.
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| /gem5/util/tlm/src/ |
| H A D | sc_master_port.cc | 282 sc_core::sc_time((double)(ticks / SimClock::Int::ps), sc_core::SC_PS);
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| /gem5/src/cpu/ |
| H A D | BaseCPU.py | 153 cpu_id = Param.Int(-1, "CPU identifier")
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| /gem5/src/systemc/tlm_bridge/ |
| H A D | tlm_to_gem5.cc | 293 sc_core::sc_time((double)(ticks / SimClock::Int::ps), sc_core::SC_PS);
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| /gem5/ext/googletest/googlemock/test/ |
| H A D | gmock-actions_test.cc | 1203 TEST(AssignTest, Int) {
1232 TEST_F(SetErrnoAndReturnTest, Int) {
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| /gem5/ext/pybind11/include/pybind11/ |
| H A D | numpy.h | 117 template <typename Concrete, typename... Check, typename... Int>
118 constexpr int platform_lookup(Int... codes) {
|