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| /gem5/src/cpu/ | ||
| H A D | base_dyn_inst.hh | diff 9932:2efeed2cef09 Thu Oct 17 11:20:00 EDT 2013 Ali Saidi <Ali.Saidi@ARM.com> cpu: Fix O3 uncacheable load that is replayed but misses the TLB This change fixes an issue in the O3 CPU where an uncachable instruction is attempted to be executed before it reaches the head of the ROB. It is determined to be uncacheable, and is replayed, but a PanicFault is attached to the instruction to make sure that it is properly executed before committing. If the TLB entry it was using is replaced in the interveaning time, the TLB returns a delayed translation when the load is replayed at the head of the ROB, however the LSQ code can't differntiate between the old fault and the new one. If the translation isn't complete it can't be faulting, so clear the fault. |
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