Searched hist:8856 (Results 1 - 5 of 5) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | tport.hh | diff 8856:241ee47b0dc6 Fri Feb 24 11:52:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Simplify cache ports preparing for master/slave split This patch splits the two cache ports into a master (memory-side) and slave (cpu-side) subclass of port with slightly different functionality. For example, it is only the CPU-side port that blocks incoming requests, and only the memory-side port that schedules send events outside of what the transmit list dictates. This patch simplifies the two classes by relying further on SimpleTimingPort and also generalises the latter to better accommodate the changes (introducing trySendTiming and scheduleSend). The memory-side cache port overrides sendDeferredPacket to be able to not only send responses from the transmit list, but also send requests based on the MSHRs. A follow on patch further simplifies the SimpleTimingPort and the cache ports. |
| H A D | tport.cc | diff 8856:241ee47b0dc6 Fri Feb 24 11:52:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Simplify cache ports preparing for master/slave split This patch splits the two cache ports into a master (memory-side) and slave (cpu-side) subclass of port with slightly different functionality. For example, it is only the CPU-side port that blocks incoming requests, and only the memory-side port that schedules send events outside of what the transmit list dictates. This patch simplifies the two classes by relying further on SimpleTimingPort and also generalises the latter to better accommodate the changes (introducing trySendTiming and scheduleSend). The memory-side cache port overrides sendDeferredPacket to be able to not only send responses from the transmit list, but also send requests based on the MSHRs. A follow on patch further simplifies the SimpleTimingPort and the cache ports. |
| /gem5/src/mem/cache/ | ||
| H A D | cache.hh | diff 8856:241ee47b0dc6 Fri Feb 24 11:52:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Simplify cache ports preparing for master/slave split This patch splits the two cache ports into a master (memory-side) and slave (cpu-side) subclass of port with slightly different functionality. For example, it is only the CPU-side port that blocks incoming requests, and only the memory-side port that schedules send events outside of what the transmit list dictates. This patch simplifies the two classes by relying further on SimpleTimingPort and also generalises the latter to better accommodate the changes (introducing trySendTiming and scheduleSend). The memory-side cache port overrides sendDeferredPacket to be able to not only send responses from the transmit list, but also send requests based on the MSHRs. A follow on patch further simplifies the SimpleTimingPort and the cache ports. |
| H A D | base.hh | diff 8856:241ee47b0dc6 Fri Feb 24 11:52:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Simplify cache ports preparing for master/slave split This patch splits the two cache ports into a master (memory-side) and slave (cpu-side) subclass of port with slightly different functionality. For example, it is only the CPU-side port that blocks incoming requests, and only the memory-side port that schedules send events outside of what the transmit list dictates. This patch simplifies the two classes by relying further on SimpleTimingPort and also generalises the latter to better accommodate the changes (introducing trySendTiming and scheduleSend). The memory-side cache port overrides sendDeferredPacket to be able to not only send responses from the transmit list, but also send requests based on the MSHRs. A follow on patch further simplifies the SimpleTimingPort and the cache ports. |
| H A D | base.cc | diff 8856:241ee47b0dc6 Fri Feb 24 11:52:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Simplify cache ports preparing for master/slave split This patch splits the two cache ports into a master (memory-side) and slave (cpu-side) subclass of port with slightly different functionality. For example, it is only the CPU-side port that blocks incoming requests, and only the memory-side port that schedules send events outside of what the transmit list dictates. This patch simplifies the two classes by relying further on SimpleTimingPort and also generalises the latter to better accommodate the changes (introducing trySendTiming and scheduleSend). The memory-side cache port overrides sendDeferredPacket to be able to not only send responses from the transmit list, but also send requests based on the MSHRs. A follow on patch further simplifies the SimpleTimingPort and the cache ports. |
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