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/gem5/configs/example/
H A Dmemtest.pydiff 11198:8149b36b8803 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> config: Update memtest to stress test cache clusivity

This patch adds an new twist to the memtest cache hierarchy, in that
it switches from mostly inclusive to mostly exclusive at every level
in the tree. This has helped weed out plenty issues, and serves as a
good stress tests.
/gem5/src/arch/arm/linux/
H A Dprocess.ccdiff 8149:12bd3ad81f9d Thu Mar 17 20:20:00 EDT 2011 Chris Emmons <Chris.Emmons@ARM.com> ARM: Add minimal ARM_SE support for m5threads.

Updated some of the assembly code sequences to use armv7 instructions and
coprocessor 15 for storing the TLS pointer.
/gem5/src/sim/
H A Dsyscall_emul.ccdiff 8149:12bd3ad81f9d Thu Mar 17 20:20:00 EDT 2011 Chris Emmons <Chris.Emmons@ARM.com> ARM: Add minimal ARM_SE support for m5threads.

Updated some of the assembly code sequences to use armv7 instructions and
coprocessor 15 for storing the TLS pointer.
H A Dsyscall_emul.hhdiff 8149:12bd3ad81f9d Thu Mar 17 20:20:00 EDT 2011 Chris Emmons <Chris.Emmons@ARM.com> ARM: Add minimal ARM_SE support for m5threads.

Updated some of the assembly code sequences to use armv7 instructions and
coprocessor 15 for storing the TLS pointer.

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