Searched hist:8142 (Results 1 - 6 of 6) sorted by relevance
/gem5/src/arch/arm/isa/insts/ | ||
H A D | m5ops.isa | diff 8142:e08035e1a1f6 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Allow conditional quiesce instructions. This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage. |
H A D | misc.isa | diff 8142:e08035e1a1f6 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Allow conditional quiesce instructions. This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage. |
/gem5/src/arch/arm/isa/templates/ | ||
H A D | pred.isa | diff 8142:e08035e1a1f6 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Allow conditional quiesce instructions. This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage. |
/gem5/src/sim/ | ||
H A D | pseudo_inst.hh | diff 8142:e08035e1a1f6 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Allow conditional quiesce instructions. This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage. |
H A D | pseudo_inst.cc | diff 8142:e08035e1a1f6 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Allow conditional quiesce instructions. This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage. |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | aarch64.isa | diff 12523:11d2f59d3b27 Thu Feb 08 13:18:00 EST 2018 Andreas Sandberg <andreas.sandberg@arm.com> arch-arm: Decode Brk64 instructions The brk instruction in aarch64 was decoded as an unimplemented instruction. Fix that. Change-Id: I3eb36a016ab56d882426c5cdef3a0b594de0f9cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8142 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
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