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/gem5/src/arch/sparc/ | ||
H A D | isa.cc | diff 6337:cac56cd6b015 Fri Jul 10 04:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Set up a lookup table for integer register flattening. Using a look up table changed the run time of the SPARC_FS solaris boot regression from: real 14m45.951s user 13m57.528s sys 0m3.452s to: real 12m19.777s user 12m2.685s sys 0m2.420s |
H A D | isa.hh | diff 6337:cac56cd6b015 Fri Jul 10 04:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Set up a lookup table for integer register flattening. Using a look up table changed the run time of the SPARC_FS solaris boot regression from: real 14m45.951s user 13m57.528s sys 0m3.452s to: real 12m19.777s user 12m2.685s sys 0m2.420s |
H A D | utility.cc | diff 6337:cac56cd6b015 Fri Jul 10 04:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Set up a lookup table for integer register flattening. Using a look up table changed the run time of the SPARC_FS solaris boot regression from: real 14m45.951s user 13m57.528s sys 0m3.452s to: real 12m19.777s user 12m2.685s sys 0m2.420s |
H A D | process.cc | diff 6337:cac56cd6b015 Fri Jul 10 04:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Set up a lookup table for integer register flattening. Using a look up table changed the run time of the SPARC_FS solaris boot regression from: real 14m45.951s user 13m57.528s sys 0m3.452s to: real 12m19.777s user 12m2.685s sys 0m2.420s |
/gem5/src/arch/arm/ | ||
H A D | isa.hh | diff 13114:777d445423d6 Mon Sep 24 04:55:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Init AArch64 ID registers in SE mode One of the auxv vector's flag is the HWCAP, whose bits match the content of several arm ID registers. This patch factors out AArch64 ID registers init into a separate method and creates the symmetric AArch32 ID register init as well, so that we get a meaningful auxiliary vector in SE mode. Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13064 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | isa.cc | diff 13114:777d445423d6 Mon Sep 24 04:55:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Init AArch64 ID registers in SE mode One of the auxv vector's flag is the HWCAP, whose bits match the content of several arm ID registers. This patch factors out AArch64 ID registers init into a separate method and creates the symmetric AArch32 ID register init as well, so that we get a meaningful auxiliary vector in SE mode. Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13064 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/sim/ | ||
H A D | syscall_emul.cc | diff 6337:cac56cd6b015 Fri Jul 10 04:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Set up a lookup table for integer register flattening. Using a look up table changed the run time of the SPARC_FS solaris boot regression from: real 14m45.951s user 13m57.528s sys 0m3.452s to: real 12m19.777s user 12m2.685s sys 0m2.420s |
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