Searched hist:7760 (Results 1 - 8 of 8) sorted by relevance
| /gem5/src/arch/arm/isa/insts/ | ||
| H A D | div.isa | diff 7760:e93e7e0caae1 Mon Nov 15 15:04:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. |
| H A D | mult.isa | diff 7760:e93e7e0caae1 Mon Nov 15 15:04:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. |
| H A D | neon.isa | diff 7760:e93e7e0caae1 Mon Nov 15 15:04:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. |
| H A D | fp.isa | diff 7760:e93e7e0caae1 Mon Nov 15 15:04:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. |
| /gem5/src/cpu/o3/ | ||
| H A D | FUPool.py | diff 7760:e93e7e0caae1 Mon Nov 15 15:04:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. |
| H A D | FuncUnitConfig.py | diff 7760:e93e7e0caae1 Mon Nov 15 15:04:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. |
| /gem5/src/cpu/ | ||
| H A D | FuncUnit.py | diff 7760:e93e7e0caae1 Mon Nov 15 15:04:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. |
| H A D | op_class.hh | diff 7760:e93e7e0caae1 Mon Nov 15 15:04:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. |
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