Searched hist:7669 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/mem/cache/ | ||
| H A D | mshr.cc | diff 7669:cc222ba29079 Thu Sep 09 14:40:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cache: fail SC when invalidated while waiting for bus Corrects an oversight in cset f97b62be544f. The fix there only failed queued SCUpgradeReq packets that encountered an invalidation, which meant that the upgrade had to reach the L2 cache. To handle pending requests in the L1 we must similarly fail StoreCondReq packets too. |
| /gem5/src/mem/ | ||
| H A D | packet.cc | diff 7669:cc222ba29079 Thu Sep 09 14:40:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cache: fail SC when invalidated while waiting for bus Corrects an oversight in cset f97b62be544f. The fix there only failed queued SCUpgradeReq packets that encountered an invalidation, which meant that the upgrade had to reach the L2 cache. To handle pending requests in the L1 we must similarly fail StoreCondReq packets too. |
| H A D | packet.hh | diff 7669:cc222ba29079 Thu Sep 09 14:40:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cache: fail SC when invalidated while waiting for bus Corrects an oversight in cset f97b62be544f. The fix there only failed queued SCUpgradeReq packets that encountered an invalidation, which meant that the upgrade had to reach the L2 cache. To handle pending requests in the L1 we must similarly fail StoreCondReq packets too. |
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