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/gem5/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/
H A Dstats.txtdiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/src/proto/
H A Dpacket.protodiff 11247:76f75db08e09 Mon Dec 07 17:42:00 EST 2015 Radhika Jagtap <radhika.jagtap@ARM.com> proto, probe: Add elastic trace probe to o3 cpu

The elastic trace is a type of probe listener and listens to probe points
in multiple stages of the O3CPU. The notify method is called on a probe
point typically when an instruction successfully progresses through that
stage.

As different listener methods mapped to the different probe points execute,
relevant information about the instruction, e.g. timestamps and register
accesses, are captured and stored in temporary InstExecInfo class objects.
When the instruction progresses through the commit stage, the timing and the
dependency information about the instruction is finalised and encapsulated in
a struct called TraceInfo. TraceInfo objects are collected in a list instead
of writing them out to the trace file one a time. This is required as the
trace is processed in chunks to evaluate order dependencies and computational
delay in case an instruction does not have any register dependencies. By this
we achieve a simpler algorithm during replay because every record in the
trace can be hooked onto a record in its past. The instruction dependency
trace is written out as a protobuf format file. A second trace containing
fetch requests at absolute timestamps is written to a separate protobuf
format file.

If the instruction is not executed then it is not added to the trace.
The code checks if the instruction had a fault, if it predicated
false and thus previous register values were restored or if it was a
load/store that did not have a request (e.g. when the size of the
request is zero). In all these cases the instruction is set as
executed by the Execute stage and is picked up by the commit probe
listener. But a request is not issued and registers are not written.
So practically, skipping these should not hurt the dependency modelling.

If squashing results in squashing younger instructions, it may happen that
the squash probe discards the inst and removes it from the temporary
store but execute stage deals with the instruction in the next cycle which
results in the execute probe seeing this inst as 'new' inst. A sequence
number of the last processed trace record is used to trap these cases and
not add to the temporary store.

The elastic instruction trace and fetch request trace can be read in and
played back by the TraceCPU.
/gem5/src/sim/
H A Ddrain.ccdiff 11859:76c36516e0ae Sun Feb 19 05:30:00 EST 2017 Andreas Hansson <andreas.hansson@arm.com> sim: Ensure draining is deterministic

The traversal of drainable objects could potentially be
non-deterministic when using an unordered set containing object
pointers. To ensure that the iteration is deterministic, we switch to
a vector. Note that the lookup and traversal of the drainable objects
is not performance critical, so the change has no negative consequences.
H A Ddrain.hhdiff 11859:76c36516e0ae Sun Feb 19 05:30:00 EST 2017 Andreas Hansson <andreas.hansson@arm.com> sim: Ensure draining is deterministic

The traversal of drainable objects could potentially be
non-deterministic when using an unordered set containing object
pointers. To ensure that the iteration is deterministic, we switch to
a vector. Note that the lookup and traversal of the drainable objects
is not performance critical, so the change has no negative consequences.
/gem5/src/systemc/core/
H A Dsc_port.ccdiff 13203:76ee4971fd9e Tue Sep 11 19:16:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add some error checks to some classes.

These check whether those classes are being constructed in legal
circumstances, and avoids a null pointer dereference.

Change-Id: Ied36ee15c3d7bf6ee444351a841c38576780298e
Reviewed-on: https://gem5-review.googlesource.com/c/12622
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/dev/mips/
H A Dmalta_cchip.ccdiff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
/gem5/src/arch/arm/
H A Dpmu.hhdiff 13638:76cb1cecc057 Thu Jan 31 04:52:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Allow ArmPPI usage for PMU

Differently from ArmSPIs, ArmPPI interrupts need to be instantiated by
giving a ThreadContext pointer in the ArmPPIGen::get() method. Since the
PMU is registering the ThreadContext only at ISA startup time, ArmPPI
generation in deferred until the PMU has a non NULL pointer.

Change-Id: I17daa6f0e355363b8778d707b440cab9f75aaea2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16204
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/systemc/tests/
H A Dworking.filtdiff 12910:76b4a4e55a37 Fri Jun 15 20:30:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Exclude another test which exercises sc_string.

Change-Id: Ic05fe3d34ef403dd6ad9348478f73c6ed50cc7bc
Reviewed-on: https://gem5-review.googlesource.com/11264
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/cpu/
H A Dcpuevent.hh2651:76db2c628241 Mon May 29 18:24:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Create a new CpuEvent class that has a pointer to an execution context in the object and places itself on a global list so
so the events can be migrated on cpu switches.
Create a new wrapper classe called CpuEventWrapper that works like the old wrapper class but calls the function with the xc
parameter
Use new CpuEventWrapper class from tick compare events on sparc

src/arch/sparc/regfile.hh:
Use new CpuEventWrapper class from tick compare events
src/arch/sparc/ua2005.cc:
Move definition to to a fullsystem only file, since it is.
src/cpu/base.cc:
On switch from one cpu to another CpuEvent::replaceExecContext() needs to be called on all (oldxc,newxc) pairs.
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/se/00.hello/ref/arm/linux/minor-timing/
H A Dstats.txtdiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/quick/se/00.hello/ref/x86/linux/o3-timing/
H A Dconfig.inidiff 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/src/dev/alpha/
H A Dbackdoor.ccdiff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
/gem5/src/dev/sparc/
H A Diob.ccdiff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
/gem5/tests/configs/
H A Dsimple-atomic.pydiff 4390:76bbcf725852 Sun Apr 22 14:39:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Update configs to set the CPU clock properly.

Completed in 146 milliseconds

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