Searched hist:7421 (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/arm/isa/formats/ | ||
| H A D | uncond.isa | diff 7421:9962b65e6b1f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make sure undefined unconditional ARM instructions decode as such. |
| /gem5/src/sim/ | ||
| H A D | system.cc | diff 12443:0479f5e6f8bd Fri Jan 12 19:16:00 EST 2018 Gabe Black <gabeblack@google.com> sim: Simplify registerThreadContext a little bit. The code in this function was a little convoluted. This change attempts to simplify it a little bit to make it easier to read. Change-Id: I1ae557b9fede47fa89a9ea550bd0af8ad242449f Reviewed-on: https://gem5-review.googlesource.com/7421 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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