Searched hist:7364 (Results 1 - 4 of 4) sorted by relevance
| /gem5/src/arch/arm/isa/insts/ | ||
| H A D | fp.isa | diff 7364:9d34477e6adb Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the VFP version of vmul. |
| /gem5/src/arch/arm/isa/formats/ | ||
| H A D | fp.isa | diff 7364:9d34477e6adb Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the VFP version of vmul. |
| /gem5/src/arch/arm/insts/ | ||
| H A D | static_inst.hh | diff 7364:9d34477e6adb Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the VFP version of vmul. |
| /gem5/src/cpu/ | ||
| H A D | BaseCPU.py | diff 12440:e028053ee1fc Thu Nov 30 10:48:00 EST 2017 Xiaoyu Ma <xiaoyuma@google.com> sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy(). Before this CL, the addTwoLevelCacheHierarchy() function uses the default L2XBar class as the interconnect between CPU L1 caches and L2. This CL allows passing a user-defined bus to overwrite the default L2XBar by adding an optional argument to the function. Change-Id: I917657272fd4924ee0bed882a226851afba26847 Reviewed-on: https://gem5-review.googlesource.com/7364 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
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