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/gem5/src/sim/
H A Dsyscall_desc.ccdiff 11994:211df6a05c5e Tue May 02 13:56:00 EDT 2017 Alexandru Dutu <alexandru.dutu@amd.com> syscall_emul: Argument retrieval bug fix

This commit fixes a stack-buffer underflow
by fixing the way the array is indexed.

Change-Id: I44400e2b99a2f8e1f48f673cd110b9dcd6480a72
Reviewed-on: https://gem5-review.googlesource.com/3040
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
H A Dclocked_object.hhdiff 9550:e0e2c8f83d08 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix up numerous warnings about name shadowing

This patch address the most important name shadowing warnings (as
produced when using gcc/clang with -Wshadow). There are many
locations where constructor parameters and function parameters shadow
local variables, but these are left unchanged.
diff 9545:508784fad4e5 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> sim: Make clock private and access using clockPeriod()

This patch makes the clock member private to the ClockedObject and
forces all children to access it using clockPeriod(). This makes it
impossible to inadvertently change the clock, and also makes it easier
to transition to a situation where the clock is derived from e.g. a
clock domain, or through a multiplier.
H A Dclock_domain.hhdiff 10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
H A Dclock_domain.ccdiff 10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
/gem5/src/mem/ruby/profiler/
H A DAddressProfiler.hhdiff 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.
/gem5/src/base/stats/
H A Dtext.hhdiff 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.
/gem5/src/dev/arm/
H A Dsmmu_v3_transl.ccdiff 14064:870553bad072 Tue Jun 18 11:56:00 EDT 2019 Adrian Herrera <adrian.herrera@arm.com> dev-arm: drain implementation for SMMUv3

SMMUv3 is drained when (1) no SMMU translations are pending
on any of its slave interfaces and (2) no commands are stored
in the Command Queue waiting to be processed.

Change-Id: I81cef5fd821fa5e509e130af02aece5239493df5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19309
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dsmmu_v3_slaveifc.ccdiff 14064:870553bad072 Tue Jun 18 11:56:00 EDT 2019 Adrian Herrera <adrian.herrera@arm.com> dev-arm: drain implementation for SMMUv3

SMMUv3 is drained when (1) no SMMU translations are pending
on any of its slave interfaces and (2) no commands are stored
in the Command Queue waiting to be processed.

Change-Id: I81cef5fd821fa5e509e130af02aece5239493df5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19309
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/dev/x86/
H A Di8259.hhdiff 9807:63d7362bbdf2 Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev: consistently end device classes in 'Device'

PciDev and IntDev stuck out as the only device classes that
ended in 'Dev' rather than 'Device'. This patch takes care
of that inconsistency.

Note that you may need to delete pre-existing files matching
build/*/python/m5/internal/param_* as scons does not pick up
indirect dependencies on imported python modules when generating
params, and the PciDev -> PciDevice rename takes place in a
file (dev/Device.py) that gets imported quite a bit.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
H A Di82094aa.ccdiff 9807:63d7362bbdf2 Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev: consistently end device classes in 'Device'

PciDev and IntDev stuck out as the only device classes that
ended in 'Dev' rather than 'Device'. This patch takes care
of that inconsistency.

Note that you may need to delete pre-existing files matching
build/*/python/m5/internal/param_* as scons does not pick up
indirect dependencies on imported python modules when generating
params, and the PciDev -> PciDevice rename takes place in a
file (dev/Device.py) that gets imported quite a bit.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
diff 9805:a4339e26b429 Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> devices: make more classes derive from BasicPioDevice
A couple of devices that have single fixed memory mapped regions
were not derived from BasicPioDevice, when that's exactly
the functionality that BasicPioDevice provides. This patch
gets rid of a little bit of redundant code by making those
devices actually do so.

Also fixed the weird case of X86ISA::Interrupts, where
the class already did derive from BasicPioDevice but
didn't actually use all the features it could have.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
H A Di82094aa.hhdiff 9807:63d7362bbdf2 Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev: consistently end device classes in 'Device'

PciDev and IntDev stuck out as the only device classes that
ended in 'Dev' rather than 'Device'. This patch takes care
of that inconsistency.

Note that you may need to delete pre-existing files matching
build/*/python/m5/internal/param_* as scons does not pick up
indirect dependencies on imported python modules when generating
params, and the PciDev -> PciDevice rename takes place in a
file (dev/Device.py) that gets imported quite a bit.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
diff 9805:a4339e26b429 Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> devices: make more classes derive from BasicPioDevice
A couple of devices that have single fixed memory mapped regions
were not derived from BasicPioDevice, when that's exactly
the functionality that BasicPioDevice provides. This patch
gets rid of a little bit of redundant code by making those
devices actually do so.

Also fixed the weird case of X86ISA::Interrupts, where
the class already did derive from BasicPioDevice but
didn't actually use all the features it could have.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/
H A Dstats.txtdiff 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000

arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes

This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/
H A Dstats.txtdiff 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000

arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes

This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
/gem5/src/cpu/testers/traffic_gen/
H A Dtraffic_gen.hhdiff 11491:6ffc99023568 Thu May 26 06:56:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> cpu: Add a basic progress check to the TrafficGen

This patch adds a progress check to the TrafficGen so that it is
easier to detect deadlock scenarios where the generator gets stuck
waiting for a retry, and makes no further progress.

Change-Id: Ifb8779ad0939f52c0518d0e867bac73f99b82e2b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
diff 9557:8666e81607a6 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix warnings issued by clang 3.2svn (XCode 4.6)

This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.
/gem5/src/mem/cache/tags/
H A Dbase_set_assoc.ccdiff 12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
diff 11486:f09bb73b3050 Thu May 26 06:56:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: fix headers include order in the cache related classes

Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/dev/
H A DSConscriptdiff 13227:8fe2a1bdc193 Thu Oct 11 20:56:00 EDT 2018 Gabe Black <gabeblack@google.com> dev: Include the platform base class even in NULL_ISA builds.

These classes don't have any ISA specific aspects.

Change-Id: Ifefb12d23e4aee8e3fd56f0a1eb3d9ad00e733a0
Reviewed-on: https://gem5-review.googlesource.com/c/13467
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff 3543:0c6fca031c44 Mon Nov 06 19:56:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Get rid of pcifake.cc and tsunami_fake.cc to go with the merged default devices.
/gem5/tests/configs/
H A Dpc-simple-atomic.pydiff 9961:1991dd858e47 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> test: Use SimpleMemory for atomic full-system tests

Keep it simple and use the SimpleMemory rather than the DRAM
controller model for atomic full-system tests.
H A Drealview-simple-atomic-dual.pydiff 9961:1991dd858e47 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> test: Use SimpleMemory for atomic full-system tests

Keep it simple and use the SimpleMemory rather than the DRAM
controller model for atomic full-system tests.
/gem5/
H A DREADMEdiff 1028:8cb77c937933 Wed Jul 28 17:56:00 EDT 2004 Ali Saidi <saidi@eecs.umich.edu> updated readme to reflect linux/scons changes
Put correct date in copyright headers based on bk changesets

LICENSE:
Updated copyright on license file
README:
Updaded readme to reflect shift to scons and linux support
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
updated copyright (only changeset in 2004)
kern/kernel_stats.cc:
kern/kernel_stats.hh:
updated copyright
/gem5/src/dev/alpha/
H A Dtsunami_io.hhdiff 9557:8666e81607a6 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix warnings issued by clang 3.2svn (XCode 4.6)

This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.
/gem5/src/mem/ruby/common/
H A DAddress.hhdiff 7054:7d6862b80049 Wed Mar 31 19:56:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: another ruby style pass
/gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/
H A Dstats.txtdiff 9962:7aef35367a21 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats after shifting to SimpleMemory

Match stats with new regression configs.
/gem5/src/cpu/
H A Dactivity.ccdiff 5804:34fe9bbc6705 Wed Jan 21 17:56:00 EST 2009 Nathan Binkert <nate@binkert.org> o3cpu: give a name to the activity recorder for better tracing
/gem5/src/cpu/o3/
H A Dfu_pool.ccdiff 9550:e0e2c8f83d08 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix up numerous warnings about name shadowing

This patch address the most important name shadowing warnings (as
produced when using gcc/clang with -Wshadow). There are many
locations where constructor parameters and function parameters shadow
local variables, but these are left unchanged.
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/
H A Dstats.txtdiff 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000

arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

Completed in 165 milliseconds

1234567891011>>