Searched hist:5058 (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/x86/isa/
H A Dincludes.isadiff 5058:be23162b7370 Thu Sep 06 19:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add SSE comparison instructions and microops and move some FP microops to be with the other ones.
/gem5/src/arch/arm/
H A Dmiscregs.ccdiff 12240:cb3c69c2d2bf Mon Sep 25 11:43:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1

A program running in EL0 is allowed to execute CMOs when the UCI bit
in SCTLR is set. The execution of dc ivac, however, would fault
uncoditionally when executed from EL0. This change aligns the
permission checks for dc ivac with the rest of the CMOs.

Change-Id: I1a532f37707c7dc0748b4375252c6ec0bbf95419
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5058
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/arch/x86/isa/microops/
H A Dregop.isadiff 5058:be23162b7370 Thu Sep 06 19:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add SSE comparison instructions and microops and move some FP microops to be with the other ones.
/gem5/src/arch/x86/isa/decoder/
H A Dtwo_byte_opcodes.isadiff 5058:be23162b7370 Thu Sep 06 19:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add SSE comparison instructions and microops and move some FP microops to be with the other ones.

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