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/gem5/util/
H A Dhgfilesize.pydiff 8680:508bbec99e58 Wed Jan 11 01:50:00 EST 2012 Nathan Binkert <nate@binkert.org> hgfilesize: skip files that have been removed
/gem5/src/arch/hsail/
H A DBrig_new.hppdiff 11737:50eceddc2286 Fri Dec 02 18:01:00 EST 2016 Brandon Potter <brandon.potter@amd.com> hsail: add popcount type and generate popcount instructions
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/
H A Dmove_with_duplication.pydiff 6565:b7f5a02ea9b7 Mon Aug 17 21:50:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the MOVDDUP instruction.
/gem5/src/arch/x86/bios/
H A DSConscriptdiff 5615:1c4b9b1aa500 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Turn SMBios structures into simobjects.
diff 5614:2e7dbd0c4a2b Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add a couple comments to the bios SConscript
5612:1bd333953e49 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Move the smbios objects into a folder for BIOS objects.
H A DSMBios.py5615:1c4b9b1aa500 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Turn SMBios structures into simobjects.
H A Dsmbios.hhdiff 5615:1c4b9b1aa500 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Turn SMBios structures into simobjects.
5612:1bd333953e49 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Move the smbios objects into a folder for BIOS objects.
/gem5/src/cpu/testers/directedtest/
H A DSConscriptdiff 8492:1ad244a20877 Mon Aug 08 11:50:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.
/gem5/src/cpu/testers/rubytest/
H A DSConscriptdiff 8492:1ad244a20877 Mon Aug 08 11:50:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/
H A Dsimerr10515:bd7c2aa12122 Thu Oct 30 00:50:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Add 64-bit ARM regression tests
/gem5/src/systemc/tests/systemc/kernel/sc_time/test14/
H A Dexpected_returncode13152:db311498b28f Sat Sep 01 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Mark a test as expected to fail/report an error.

Change-Id: Ia5e22000449e233a079d8ba7d777a3d030138a44
Reviewed-on: https://gem5-review.googlesource.com/c/12464
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/mem/
H A DDRAMSim2.py10066:06a33d872798 Tue Feb 18 05:50:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add a wrapped DRAMSim2 memory controller

This patch adds DRAMSim2 as a memory controller by wrapping the
external library and creating a sublass of AbstractMemory that bridges
between the semantics of gem5 and the DRAMSim2 interface.

The DRAMSim2 wrapper extracts the clock period from the config
file. There is no way of extracting this information from DRAMSim2
itself, so we simply read the same config file and get it from there.

To properly model the response queue, the wrapper keeps track of how
many transactions are in the actual controller, and how many are
stacking up waiting to be sent back as responses (in the wrapper). The
latter requires us to move away from the queued port and manage the
packets ourselves. This is due to DRAMSim2 not having any flow control
on the response path.

DRAMSim2 assumes that the transactions it is given are matching the
burst size of the choosen memory. The wrapper checks to ensure the
cache line size of the system matches the burst size of DRAMSim2 as
there are currently no provisions to split the system requests. In
theory we could allow a cache line size smaller than the burst size,
but that would lead to inefficient use of the DRAM, so for not we
fatal also in this case.
H A Ddramsim2_wrapper.hh10066:06a33d872798 Tue Feb 18 05:50:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add a wrapped DRAMSim2 memory controller

This patch adds DRAMSim2 as a memory controller by wrapping the
external library and creating a sublass of AbstractMemory that bridges
between the semantics of gem5 and the DRAMSim2 interface.

The DRAMSim2 wrapper extracts the clock period from the config
file. There is no way of extracting this information from DRAMSim2
itself, so we simply read the same config file and get it from there.

To properly model the response queue, the wrapper keeps track of how
many transactions are in the actual controller, and how many are
stacking up waiting to be sent back as responses (in the wrapper). The
latter requires us to move away from the queued port and manage the
packets ourselves. This is due to DRAMSim2 not having any flow control
on the response path.

DRAMSim2 assumes that the transactions it is given are matching the
burst size of the choosen memory. The wrapper checks to ensure the
cache line size of the system matches the burst size of DRAMSim2 as
there are currently no provisions to split the system requests. In
theory we could allow a cache line size smaller than the burst size,
but that would lead to inefficient use of the DRAM, so for not we
fatal also in this case.
/gem5/ext/dramsim2/
H A DREADME10066:06a33d872798 Tue Feb 18 05:50:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add a wrapped DRAMSim2 memory controller

This patch adds DRAMSim2 as a memory controller by wrapping the
external library and creating a sublass of AbstractMemory that bridges
between the semantics of gem5 and the DRAMSim2 interface.

The DRAMSim2 wrapper extracts the clock period from the config
file. There is no way of extracting this information from DRAMSim2
itself, so we simply read the same config file and get it from there.

To properly model the response queue, the wrapper keeps track of how
many transactions are in the actual controller, and how many are
stacking up waiting to be sent back as responses (in the wrapper). The
latter requires us to move away from the queued port and manage the
packets ourselves. This is due to DRAMSim2 not having any flow control
on the response path.

DRAMSim2 assumes that the transactions it is given are matching the
burst size of the choosen memory. The wrapper checks to ensure the
cache line size of the system matches the burst size of DRAMSim2 as
there are currently no provisions to split the system requests. In
theory we could allow a cache line size smaller than the burst size,
but that would lead to inefficient use of the DRAM, so for not we
fatal also in this case.
/gem5/src/arch/arm/isa/
H A Dmain.isadiff 6254:8abc40611938 Mon Jun 22 01:50:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Move util functions out of the isa desc.
/gem5/src/arch/power/isa/formats/
H A Dutil.isadiff 7045:e21fe6a62b1c Tue Mar 23 11:50:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cpu: fix exec tracing memory corruption bug
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.

It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical. Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.

This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition. It also moves those calls above
the translation calls to eliminate the crashes.
/gem5/src/arch/x86/isa/insts/x87/arithmetic/
H A Daddition.pydiff 10044:42e058cae3d0 Mon Jan 27 19:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> x86: implements x87 add/sub instructions
H A Dsubtraction.pydiff 10044:42e058cae3d0 Mon Jan 27 19:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> x86: implements x87 add/sub instructions
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/
H A Dexchange.pydiff 10043:301f2c0b3423 Mon Jan 27 19:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> x86: implements fxch instruction.
/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/
H A Dsimerrdiff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/
H A Dsimerr10515:bd7c2aa12122 Thu Oct 30 00:50:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Add 64-bit ARM regression tests
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/
H A Dsimerr10515:bd7c2aa12122 Thu Oct 30 00:50:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Add 64-bit ARM regression tests
/gem5/util/systemc/systemc_within_gem5/systemc_sc_main/
H A Dsc_main.ccdiff 13498:f6fb1bbfa39e Mon Dec 17 10:50:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> systemc: Allow specific functions to shadow the base class method

sc_in::bind and sc_core::sc_object::print shadow their respective base
class method. This change adds the necessary declarations to inform
the compiler that this is intentional.

Change-Id: I8c6bc0f05aa568630783db63d52be90f4ea4748c
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15135
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/base/
H A Daddr_range.test.ccdiff 14048:9fca1b5cea8b Sun May 26 18:50:00 EDT 2019 Nikos Nikoleris <nikos.nikoleris@arm.com> base: Extend unit tests for AddrRange

Change-Id: Ia154c3a17c3c8254a0e3d622568ac34f0d62fc9e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19131
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/
H A D.hgignorediff 10066:06a33d872798 Tue Feb 18 05:50:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add a wrapped DRAMSim2 memory controller

This patch adds DRAMSim2 as a memory controller by wrapping the
external library and creating a sublass of AbstractMemory that bridges
between the semantics of gem5 and the DRAMSim2 interface.

The DRAMSim2 wrapper extracts the clock period from the config
file. There is no way of extracting this information from DRAMSim2
itself, so we simply read the same config file and get it from there.

To properly model the response queue, the wrapper keeps track of how
many transactions are in the actual controller, and how many are
stacking up waiting to be sent back as responses (in the wrapper). The
latter requires us to move away from the queued port and manage the
packets ourselves. This is due to DRAMSim2 not having any flow control
on the response path.

DRAMSim2 assumes that the transactions it is given are matching the
burst size of the choosen memory. The wrapper checks to ensure the
cache line size of the system matches the burst size of DRAMSim2 as
there are currently no provisions to split the system requests. In
theory we could allow a cache line size smaller than the burst size,
but that would lead to inefficient use of the DRAM, so for not we
fatal also in this case.
4677:50d1e67c44ec Sat Jul 14 01:39:00 EDT 2007 Nathan Binkert <nate@binkert.org> ignore stuff that we don't want to see in the status
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/
H A Dsimoutdiff 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000

arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
diff 10848:e61f847e74fd Sat May 23 08:50:00 EDT 2015 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm, stats: Update stats to reflect changes to generic timer

The addition of a virtual timer affects stats in minor and o3.

Completed in 39 milliseconds

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